- Timestamp:
- Jul 10, 2014, 2:35:05 PM (10 years ago)
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branches/reconfiguration/platforms/tsar_generic_iob/arch.py
r747 r748 8 8 # author : Alain Greiner 9 9 ####################################################################################### 10 # This file contains a mapping generator for the "tsar_generic_iob" platform. 10 # This file contains a mapping generator for the "tsar_generic_iob" platform. 11 11 # This includes both the hardware architecture (clusters, processors, peripherals, 12 12 # physical space segmentation) and the mapping of all kernel objects (global vsegs). … … 42 42 43 43 nb_ttys = 1 44 nb_nics = 2 44 nb_nics = 2 45 45 fbf_width = 1024 46 46 x_io = 0 … … 53 53 peri_increment = 0x10000 54 54 distributed_ptabs = True 55 55 56 56 ### parameters checking 57 57 58 58 assert( nb_procs <= 4 ) 59 59 60 assert( (x_size == 1) or (x_size == 2) or (x_size == 4) 60 assert( (x_size == 1) or (x_size == 2) or (x_size == 4) 61 61 or (y_size == 8) or (x_size == 16) ) 62 62 63 assert( (y_size == 1) or (y_size == 2) or (y_size == 4) 63 assert( (y_size == 1) or (y_size == 2) or (y_size == 4) 64 64 or (y_size == 8) or (y_size == 16) ) 65 65 … … 70 70 71 71 platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) 72 72 73 73 ### define physical segments 74 74 75 ram_base = 0x0000000000 76 ram_size = 0x4000000 # 64 Mbytes 77 78 xcu_base = 0x00B0000000 79 xcu_size = 0x1000 # 4 Kbytes 80 81 dma_base = 0x00B1000000 82 dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs 83 84 mmc_base = 0x00B2000000 85 mmc_size = 0x1000 # 4 Kbytes 75 ram_base = 0x0000000000 76 ram_size = 0x4000000 # 64 Mbytes 77 78 xcu_base = 0x00B0000000 79 xcu_size = 0x1000 # 4 Kbytes 80 81 dma_base = 0x00B1000000 82 dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs 83 84 mmc_base = 0x00B2000000 85 mmc_size = 0x1000 # 4 Kbytes 86 87 rom_base = 0x00BFC00000 88 rom_size = 0x8000 # 32 Kbytes 86 89 87 90 offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) … … 106 109 107 110 iob_base = 0x00BE000000 + offset_io 108 iob_size = 0x1000 # 4kbytes 109 110 rom_base = 0x00BFC00000 + offset_io 111 rom_size = 0x4000 # 16 Kbytes 111 iob_size = 0x1000 # 4 kbytes 112 113 ### GIET_VM specifics virtual segments 112 114 113 115 ### define bootloader vsegs base addresses … … 117 119 118 120 boot_code_vbase = 0x00040000 # ident 119 boot_code_size = 0x00020000 # 128 Kbytes 120 121 boot_code_size = 0x00020000 # 128 Kbytes 122 121 123 boot_data_vbase = 0x00060000 # ident 122 124 boot_data_size = 0x00010000 # 64 Kbytes … … 125 127 boot_buffer_size = 0x00060000 # 384 Kbytes 126 128 127 boot_stack_vbase = 0x0 00D0000 # ident128 boot_stack_size = 0x00 050000 # 320 Kbytes129 boot_stack_vbase = 0x03F00000 # ident 130 boot_stack_size = 0x00100000 # 1 Mbytes 129 131 130 132 ### define kernel vsegs base addresses 131 133 132 kernel_code_vbase = 0x80000000 134 kernel_code_vbase = 0x80000000 133 135 kernel_code_size = 0x00020000 # 128 Kbytes 134 136 … … 147 149 ### create mapping 148 150 149 mapping = Mapping( name = platform_name, 150 x_size = x_size, 151 y_size = y_size, 152 procs_max = nb_procs, 153 x_width = x_width, 154 y_width = y_width, 155 paddr_width = paddr_width, 156 coherence = True, 157 irq_per_proc = irq_per_proc, 158 use_ramdisk = use_ramdisk, 159 x_io = x_io, 151 mapping = Mapping( name = platform_name, 152 x_size = x_size, 153 y_size = y_size, 154 procs_max = nb_procs, 155 x_width = x_width, 156 y_width = y_width, 157 paddr_width = paddr_width, 158 coherence = True, 159 irq_per_proc = irq_per_proc, 160 use_ramdisk = use_ramdisk, 161 x_io = x_io, 160 162 y_io = y_io, 161 peri_increment = peri_increment, 162 ram_base = ram_base, 163 ram_size = ram_size ) 163 peri_increment = peri_increment, 164 ram_base = ram_base, 165 ram_size = ram_size ) 164 166 165 167 ### external peripherals (accessible in cluster[0,0] only for this mapping) … … 171 173 tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) 172 174 173 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 175 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 174 176 175 177 cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) 176 178 177 179 fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = fbf_width ) 178 179 rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, ptype = 'ROM' )180 180 181 181 pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, ptype = 'PIC', channels = 32 ) … … 196 196 mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 ) 197 197 198 ### hardware components replicated in all clusters 198 ### hardware components replicated in all clusters 199 199 200 200 for x in xrange( x_size ): … … 205 205 ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) 206 206 207 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 207 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 208 208 ptype = 'MMC' ) 209 209 210 dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, 211 ptype = 'DMA', channels = nb_procs ) 212 213 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 210 dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, 211 ptype = 'DMA', channels = nb_procs ) 212 213 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 214 214 ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) 215 216 rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size, 217 ptype = 'ROM' ) 215 218 216 219 # MMC IRQ replicated in all clusters … … 221 224 mapping.addProc( x, y, p ) 222 225 223 ### global vsegs for boot_loader / identity mapping 224 225 mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, 226 'C_W_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', 227 identity = True ) 228 229 mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, 230 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 231 identity = True ) 232 233 mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, 234 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 235 identity = True ) 236 237 mapping.addGlobal( 'seg_boot_buffer', boot_buffer_vbase, boot_buffer_size, 238 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 239 identity = True ) 240 241 mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, 242 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 243 identity = True ) 244 245 ### the code global vsegs for kernel can be replicated in all clusters 246 ### if the page tables are distributed in all clusters. 226 ### global vsegs for boot_loader / identity mapping 227 228 mapping.addGlobal( 'seg_boot_mapping' , boot_mapping_vbase , boot_mapping_size , 'C_W_', 229 vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', identity = True ) 230 231 mapping.addGlobal( 'seg_boot_code' , boot_code_vbase , boot_code_size , 'CXW_', 232 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 233 234 mapping.addGlobal( 'seg_boot_data' , boot_data_vbase , boot_data_size , 'C_W_', 235 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 236 237 mapping.addGlobal( 'seg_boot_buffer' , boot_buffer_vbase , boot_buffer_size , 'C_W_', 238 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 239 240 mapping.addGlobal( 'seg_boot_stack' , boot_stack_vbase , boot_stack_size , 'C_W_', 241 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 242 243 ### global vsegs for kernel 247 244 248 245 if distributed_ptabs: … … 261 258 mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size, 262 259 'CXW_', vtype = 'ELF', x = 0 , y = 0 , pseg = 'RAM', 263 binpath = 'build/kernel/kernel.elf', local = False)260 binpath = 'build/kernel/kernel.elf' ) 264 261 265 262 mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size, 266 263 'CXW_', vtype = 'ELF', x = 0 , y = 0 , pseg = 'RAM', 267 binpath = 'build/kernel/kernel.elf', local = False ) 268 269 ### shared global vsegs for kernel 270 271 mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, 272 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 273 binpath = 'build/kernel/kernel.elf', local = False ) 274 275 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, 276 '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 277 binpath = 'build/kernel/kernel.elf', local = False ) 264 binpath = 'build/kernel/kernel.elf' ) 265 266 mapping.addGlobal( 'seg_kernel_data' , kernel_data_vbase , kernel_data_size , 'C_W_', 267 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 268 269 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', 270 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 278 271 279 272 ### global vsegs for external peripherals / identity mapping 280 273 281 mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 282 vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', 283 identity = True ) 284 285 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 286 vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', 287 identity = True ) 288 289 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 290 vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', 291 identity = True ) 292 293 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 294 vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', 295 identity = True ) 296 297 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 298 vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', 299 identity = True ) 300 301 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 302 vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', 303 identity = True ) 304 305 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 306 vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', 307 identity = True ) 308 309 mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', 310 vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', 311 identity = True ) 312 313 ### global vsegs for internal peripherals, and for schedulers 274 mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 275 vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', identity = True ) 276 277 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 278 vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', identity = True ) 279 280 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 281 vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', identity = True ) 282 283 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 284 vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', identity = True ) 285 286 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 287 vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', identity = True ) 288 289 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 290 vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', identity = True ) 291 292 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 293 vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True ) 294 295 ### global vsegs for internal peripherals, and for schedulers 314 296 ### name is indexed by (x,y) / vbase address is incremented by (cluster_xy * peri_increment) 315 297 … … 319 301 offset = cluster_xy * peri_increment 320 302 303 mapping.addGlobal( 'seg_rom_%d_%d' %(x,y), rom_base + offset, rom_size, 304 'CX__', vtype = 'PERI' , x = x , y = y , pseg = 'ROM' ) 305 321 306 mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, 322 307 '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU' ) … … 348 333 349 334 # print mapping.giet_vsegs() 350 335 351 336 352 337 # Local Variables:
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