Changeset 802
- Timestamp:
- Sep 12, 2014, 3:10:04 PM (10 years ago)
- Location:
- trunk/platforms/tsar_generic_iob
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_iob/arch.py
r770 r802 1 1 #!/usr/bin/env python 2 2 3 from math import log, ceil 3 4 from mapping import * 4 5 … … 8 9 # author : Alain Greiner 9 10 ####################################################################################### 10 # This file contains a mapping generator for the "tsar_generic_iob" platform. 11 # This file contains a mapping generator for the "tsar_generic_iob" platform. 11 12 # This includes both the hardware architecture (clusters, processors, peripherals, 12 13 # physical space segmentation) and the mapping of all kernel objects (global vsegs). … … 42 43 43 44 nb_ttys = 1 44 nb_nics = 2 45 nb_nics = 2 45 46 fbf_width = 128 46 47 x_io = 0 … … 48 49 x_width = 4 49 50 y_width = 4 51 p_width = int(ceil(log(nb_procs, 2))) 50 52 paddr_width = 40 51 53 irq_per_proc = 4 … … 53 55 peri_increment = 0x10000 54 56 distributed_ptabs = True 55 57 56 58 ### parameters checking 57 59 58 assert( nb_procs <= 4)59 60 assert( (x_size == 1) or (x_size == 2) or (x_size == 4) 60 assert( nb_procs <= (1 << p_width) ) 61 62 assert( (x_size == 1) or (x_size == 2) or (x_size == 4) 61 63 or (x_size == 8) or (x_size == 16) ) 62 64 63 assert( (y_size == 1) or (y_size == 2) or (y_size == 4) 65 assert( (y_size == 1) or (y_size == 2) or (y_size == 4) 64 66 or (y_size == 8) or (y_size == 16) ) 65 67 … … 70 72 71 73 platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) 72 74 73 75 ### define physical segments 74 76 … … 76 78 ram_size = 0x4000000 # 64 Mbytes 77 79 78 xcu_base = 0x00B0000000 79 xcu_size = 0x1000 # 4 Kbytes 80 xcu_base = 0x00B0000000 81 xcu_size = 0x1000 # 4 Kbytes 80 82 81 83 dma_base = 0x00B1000000 82 84 dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs 83 85 84 mmc_base = 0x00B2000000 86 mmc_base = 0x00B2000000 85 87 mmc_size = 0x1000 # 4 Kbytes 86 88 … … 117 119 118 120 boot_code_vbase = 0x00080000 # ident 119 boot_code_size = 0x00040000 # 256 Kbytes 120 121 boot_code_size = 0x00040000 # 256 Kbytes 122 121 123 boot_data_vbase = 0x000C0000 # ident 122 124 boot_data_size = 0x00080000 # 512 Kbytes … … 127 129 ### define kernel vsegs base addresses and sizes 128 130 129 kernel_code_vbase = 0x80000000 131 kernel_code_vbase = 0x80000000 130 132 kernel_code_size = 0x00020000 # 128 Kbytes 131 133 … … 144 146 ### create mapping 145 147 146 mapping = Mapping( name = platform_name, 147 x_size = x_size, 148 y_size = y_size, 149 procs_max = nb_procs, 150 x_width = x_width, 151 y_width = y_width, 152 paddr_width = paddr_width, 153 coherence = True, 154 irq_per_proc = irq_per_proc, 155 use_ramdisk = use_ramdisk, 156 x_io = x_io, 148 mapping = Mapping( name = platform_name, 149 x_size = x_size, 150 y_size = y_size, 151 procs_max = nb_procs, 152 x_width = x_width, 153 y_width = y_width, 154 p_width = p_width, 155 paddr_width = paddr_width, 156 coherence = True, 157 irq_per_proc = irq_per_proc, 158 use_ramdisk = use_ramdisk, 159 x_io = x_io, 157 160 y_io = y_io, 158 peri_increment = peri_increment, 159 ram_base = ram_base, 160 ram_size = ram_size ) 161 peri_increment = peri_increment, 162 ram_base = ram_base, 163 ram_size = ram_size ) 161 164 162 165 ### external peripherals (accessible in cluster[0,0] only for this mapping) … … 168 171 tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) 169 172 170 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 173 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 171 174 172 175 cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) … … 193 196 mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 ) 194 197 195 ### hardware components replicated in all clusters 198 ### hardware components replicated in all clusters 196 199 197 200 for x in xrange( x_size ): … … 202 205 ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) 203 206 204 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 207 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 205 208 ptype = 'MMC' ) 206 209 207 dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, 208 ptype = 'DMA', channels = nb_procs ) 209 210 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 210 dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, 211 ptype = 'DMA', channels = nb_procs ) 212 213 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 211 214 ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) 212 215 … … 223 226 mapping.addProc( x, y, p ) 224 227 225 ### global vsegs for boot_loader / identity mapping 228 ### global vsegs for boot_loader / identity mapping 226 229 227 230 mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, … … 241 244 identity = True ) 242 245 243 ### the code global vsegs for kernel can be replicated in all clusters 246 ### the code global vsegs for kernel can be replicated in all clusters 244 247 ### if the page tables are distributed in all clusters. 245 248 … … 267 270 ### shared global vsegs for kernel 268 271 269 mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, 270 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 272 mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, 273 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 271 274 binpath = 'build/kernel/kernel.elf', local = False ) 272 275 273 276 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, 274 '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 277 '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 275 278 binpath = 'build/kernel/kernel.elf', local = False ) 276 279 277 280 ### global vsegs for external peripherals / identity mapping 278 281 279 mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 280 vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', 281 identity = True ) 282 283 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 282 mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 283 vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', 284 identity = True ) 285 286 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 284 287 vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', 285 288 identity = True ) 286 289 287 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 290 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 288 291 vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', 289 292 identity = True ) 290 293 291 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 294 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 292 295 vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', 293 296 identity = True ) 294 297 295 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 298 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 296 299 vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', 297 300 identity = True ) 298 301 299 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 302 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 300 303 vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', 301 304 identity = True ) 302 305 303 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 306 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 304 307 vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', 305 308 identity = True ) 306 309 307 mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', 310 mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', 308 311 vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', 309 312 identity = True ) 310 313 311 ### global vsegs for internal peripherals, and for schedulers 314 ### global vsegs for internal peripherals, and for schedulers 312 315 ### name is indexed by (x,y) / vbase address is incremented by (cluster_xy * peri_increment) 313 316 … … 346 349 347 350 # print mapping.giet_vsegs() 348 351 349 352 350 353 # Local Variables: -
trunk/platforms/tsar_generic_iob/non_distributed_arch.py
r730 r802 1 1 #!/usr/bin/env python 2 2 3 from math import log, ceil 3 4 from mapping import * 4 5 … … 8 9 # author : Alain Greiner 9 10 ####################################################################################### 10 # This file contains a mapping generator for the "tsar_generic_iob" platform. 11 # This file contains a mapping generator for the "tsar_generic_iob" platform. 11 12 # This includes both the hardware architecture (clusters, processors, peripherals, 12 13 # physical space segmentation) and the mapping of all kernel objects (global vsegs). … … 42 43 43 44 nb_ttys = 1 44 nb_nics = 2 45 nb_nics = 2 45 46 fbf_width = 1024 46 47 x_io = 0 47 48 y_io = 0 49 p_width = int(ceil(log(nb_procs, 2))) 48 50 x_width = 4 49 51 y_width = 4 … … 52 54 use_ramdisk = False 53 55 peri_increment = 0x10000 54 56 55 57 ### parameters checking 56 58 57 assert( nb_procs <= 4)58 59 assert( (x_size == 1) or (x_size == 2) or (x_size == 4) 59 assert( nb_procs <= (1 << p_width) ) 60 61 assert( (x_size == 1) or (x_size == 2) or (x_size == 4) 60 62 or (y_size == 8) or (x_size == 16) ) 61 63 62 assert( (y_size == 1) or (y_size == 2) or (y_size == 4) 64 assert( (y_size == 1) or (y_size == 2) or (y_size == 4) 63 65 or (y_size == 8) or (y_size == 16) ) 64 66 … … 69 71 70 72 platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) 71 73 72 74 ### define physical segments 73 75 … … 75 77 ram_size = 0x4000000 # 64 Mbytes 76 78 77 xcu_base = 0x00B0000000 78 xcu_size = 0x1000 # 4 Kbytes 79 xcu_base = 0x00B0000000 80 xcu_size = 0x1000 # 4 Kbytes 79 81 80 82 dma_base = 0x00B1000000 81 83 dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs 82 84 83 mmc_base = 0x00B2000000 85 mmc_base = 0x00B2000000 84 86 mmc_size = 0x1000 # 4 Kbytes 85 87 … … 116 118 117 119 boot_code_vbase = 0x00010000 # ident 118 boot_code_size = 0x00020000 # 128 Kbytes 119 120 boot_code_size = 0x00020000 # 128 Kbytes 121 120 122 boot_data_vbase = 0x00030000 # ident 121 123 boot_data_size = 0x00010000 # 64 Kbytes … … 129 131 ### define kernel vsegs base addresses 130 132 131 kernel_code_vbase = 0x80000000 133 kernel_code_vbase = 0x80000000 132 134 kernel_code_size = 0x00020000 # 128 Kbytes 133 135 … … 146 148 ### create mapping 147 149 148 mapping = Mapping( name = platform_name, 149 x_size = x_size, 150 y_size = y_size, 151 procs_max = nb_procs, 152 x_width = x_width, 153 y_width = y_width, 154 paddr_width = paddr_width, 155 coherence = True, 156 irq_per_proc = irq_per_proc, 157 use_ramdisk = use_ramdisk, 158 x_io = x_io, 150 mapping = Mapping( name = platform_name, 151 x_size = x_size, 152 y_size = y_size, 153 procs_max = nb_procs, 154 x_width = x_width, 155 y_width = y_width, 156 p_width = p_width, 157 paddr_width = paddr_width, 158 coherence = True, 159 irq_per_proc = irq_per_proc, 160 use_ramdisk = use_ramdisk, 161 x_io = x_io, 159 162 y_io = y_io, 160 peri_increment = peri_increment ) 163 peri_increment = peri_increment ) 161 164 162 165 ### external peripherals (accessible in cluster[0,0] only for this mapping) … … 168 171 tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) 169 172 170 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 173 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 171 174 172 175 cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) … … 193 196 mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 ) 194 197 195 ### hardware components replicated in all clusters 198 ### hardware components replicated in all clusters 196 199 197 200 for x in xrange( x_size ): … … 202 205 ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) 203 206 204 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 207 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 205 208 ptype = 'MMC' ) 206 209 207 dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, 208 ptype = 'DMA', channels = nb_procs ) 209 210 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 210 dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, 211 ptype = 'DMA', channels = nb_procs ) 212 213 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 211 214 ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) 212 215 … … 220 223 ### global vsegs for boot_loader / identity mapping 221 224 222 mapping.addGlobal( 'seg_boot_mapping' , boot_mapping_vbase , boot_mapping_size , 'C_W_', 225 mapping.addGlobal( 'seg_boot_mapping' , boot_mapping_vbase , boot_mapping_size , 'C_W_', 223 226 vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', identity = True ) 224 227 225 mapping.addGlobal( 'seg_boot_code' , boot_code_vbase , boot_code_size , 'CXW_', 228 mapping.addGlobal( 'seg_boot_code' , boot_code_vbase , boot_code_size , 'CXW_', 226 229 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 227 230 228 mapping.addGlobal( 'seg_boot_data' , boot_data_vbase , boot_data_size , 'C_W_', 231 mapping.addGlobal( 'seg_boot_data' , boot_data_vbase , boot_data_size , 'C_W_', 229 232 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 230 233 231 mapping.addGlobal( 'seg_boot_buffer' , boot_buffer_vbase , boot_buffer_size , 'C_W_', 234 mapping.addGlobal( 'seg_boot_buffer' , boot_buffer_vbase , boot_buffer_size , 'C_W_', 232 235 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 233 236 234 mapping.addGlobal( 'seg_boot_stack' , boot_stack_vbase , boot_stack_size , 'C_W_', 237 mapping.addGlobal( 'seg_boot_stack' , boot_stack_vbase , boot_stack_size , 'C_W_', 235 238 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 236 239 237 ### global vsegs for kernel 238 239 mapping.addGlobal( 'seg_kernel_code' , kernel_code_vbase , kernel_code_size , 'CXW_', 240 ### global vsegs for kernel 241 242 mapping.addGlobal( 'seg_kernel_code' , kernel_code_vbase , kernel_code_size , 'CXW_', 240 243 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 241 244 242 mapping.addGlobal( 'seg_kernel_data' , kernel_data_vbase , kernel_data_size , 'C_W_', 245 mapping.addGlobal( 'seg_kernel_data' , kernel_data_vbase , kernel_data_size , 'C_W_', 243 246 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 244 247 245 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', 248 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', 246 249 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 247 250 248 mapping.addGlobal( 'seg_kernel_init' , kernel_init_vbase , kernel_init_size , 'CXW_', 251 mapping.addGlobal( 'seg_kernel_init' , kernel_init_vbase , kernel_init_size , 'CXW_', 249 252 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 250 253 251 254 ### global vsegs for external peripherals / identity mapping 252 255 253 mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 256 mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 254 257 vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', identity = True ) 255 258 256 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 259 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 257 260 vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', identity = True ) 258 261 259 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 262 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 260 263 vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', identity = True ) 261 264 262 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 265 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 263 266 vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', identity = True ) 264 267 265 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 268 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 266 269 vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', identity = True ) 267 270 268 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 271 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 269 272 vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', identity = True ) 270 273 271 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 274 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 272 275 vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True ) 273 276 274 mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', 277 mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', 275 278 vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', identity = True ) 276 279 277 ### Global vsegs for replicated peripherals, and for schedulers 280 ### Global vsegs for replicated peripherals, and for schedulers 278 281 ### name is indexed by (x,y), base address is incremented by (cluster_xy * peri_increment) 279 282 … … 303 306 if __name__ == '__main__': 304 307 305 mapping = genmap( x_size = 2, 306 y_size = 2, 307 nb_procs = 2, 308 nb_ttys = 1, 309 nb_nics = 2, 310 fbf_width = 128, 311 x_io = 0, 312 y_io = 0 ) 308 mapping = arch( x_size = 2, 309 y_size = 2, 310 nb_procs = 2 ) 313 311 314 312 # print mapping.netbsd_dts() … … 317 315 318 316 # print mapping.giet_vsegs() 319 317 320 318 321 319 # Local Variables: -
trunk/platforms/tsar_generic_iob/top.cpp
r765 r802 186 186 //////////////////////i///////////////////////////////////// 187 187 188 #include " ../../../giet_vm/hard_config.h"188 #include "hard_config.h" 189 189 190 190 //////////////////////////////////////////////////////////// … … 336 336 size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 337 337 size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 338 size_t x_width = 4; // at most 256 clusters 339 size_t y_width = 4; // at most 256 clusters 338 size_t x_width = X_WIDTH; // # of bits for x 339 size_t y_width = Y_WIDTH; // # of bits for y 340 size_t p_width = P_WIDTH; // # of bits for lpid 340 341 341 342 #if USING_OPENMP … … 347 348 assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and 348 349 "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); 350 351 assert( P_WIDTH <= 3 and 352 "ERROR: we must have P_WIDTH <= 3"); 349 353 350 354 ////////////// command line arguments ////////////////////// … … 399 403 { 400 404 debug_proc_id = atoi(argv[n+1]); 401 size_t cluster_xy = debug_proc_id / NB_PROCS_MAX;405 size_t cluster_xy = debug_proc_id >> P_WIDTH ; 402 406 size_t x = cluster_xy >> 4; 403 407 size_t y = cluster_xy & 0xF; … … 444 448 "The YMAX parameter cannot be larger than 16" ); 445 449 446 assert( (NB_PROCS_MAX <= 8) and447 " The NB_PROCS_MAX parameter cannot be larger than 8" );450 assert( (NB_PROCS_MAX <= (1 << P_WIDTH)) and 451 "NB_PROCS_MAX parameter cannot be larger than 2^P_WIDTH" ); 448 452 449 453 assert( (NB_DMA_CHANNELS <= 4) and … … 459 463 << " - XMAX = " << XMAX << std::endl 460 464 << " - YMAX = " << YMAX << std::endl 461 << " - NB_PROCS_MAX = " << NB_PROCS_MAX << 465 << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl 462 466 << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl 463 467 << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl … … 602 606 IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); 603 607 604 for ( size_t p = 0 ; p < NB_PROCS_MAX 608 for ( size_t p = 0 ; p < NB_PROCS_MAX; p++ ) 605 609 maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), 606 610 IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); … … 1038 1042 y_width, 1039 1043 vci_srcid_width - x_width - y_width, // l_id width, 1044 p_width, 1040 1045 1041 1046 INT_MEMC_TGT_ID, … … 1438 1443 if ( debug_proc_id != 0xFFFFFFFF ) 1439 1444 { 1440 size_t l = debug_proc_id % NB_PROCS_MAX;1441 size_t cluster_xy = debug_proc_id / NB_PROCS_MAX;1445 size_t l = debug_proc_id & ((1<<P_WIDTH)-1) ; 1446 size_t cluster_xy = debug_proc_id >> P_WIDTH ; 1442 1447 size_t x = cluster_xy >> 4; 1443 1448 size_t y = cluster_xy & 0xF; … … 1460 1465 // local interrupts in cluster(x,y) 1461 1466 if( clusters[x][y]->signal_irq_memc.read() ) 1462 std::cout << "### IRQ_MMC_" << std::dec << x << "_" << y 1467 std::cout << "### IRQ_MMC_" << std::dec << x << "_" << y 1463 1468 << " ACTIVE" << std::endl; 1464 1469 … … 1466 1471 { 1467 1472 if( clusters[x][y]->signal_irq_mdma[c].read() ) 1468 std::cout << "### IRQ_DMA_" << std::dec << x << "_" << y << "_" << c 1473 std::cout << "### IRQ_DMA_" << std::dec << x << "_" << y << "_" << c 1469 1474 << " ACTIVE" << std::endl; 1470 1475 } 1471 1476 1472 1477 for ( size_t c = 0 ; c < NB_PROCS_MAX ; c++ ) 1473 1478 { 1474 1479 if( clusters[x][y]->signal_proc_it[c].read() ) 1475 std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << c 1480 std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << c 1476 1481 << " ACTIVE" << std::endl; 1477 1482 } -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r739 r802 201 201 size_t y_width, // y field bits 202 202 size_t l_width, // l field bits 203 size_t p_width, // p field bits 203 204 204 205 size_t int_memc_tgt_id, -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r739 r802 1 1 ////////////////////////////////////////////////////////////////////////////// 2 2 // File: tsar_iob_cluster.cpp 3 // Author: Alain Greiner 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 5 // Date : april 2013 … … 10 10 // - 1 vci_io_bridge (connected to the 3 networks. 11 11 // - 3 vci_dspin_wrapper for the IOB. 12 // - 2 dspin_local_crossbar for commands and responses. 12 // - 2 dspin_local_crossbar for commands and responses. 13 13 ////////////////////////////////////////////////////////////////////////////// 14 14 … … 40 40 41 41 const soclib::common::MappingTable &mt_int, 42 const soclib::common::MappingTable &mt_ram, 43 const soclib::common::MappingTable &mt_iox, 42 const soclib::common::MappingTable &mt_ram, 43 const soclib::common::MappingTable &mt_iox, 44 44 45 45 size_t x_width, 46 46 size_t y_width, 47 47 size_t l_width, 48 size_t p_width, 48 49 49 50 size_t int_memc_tgt_id, // local index … … 103 104 { 104 105 p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; 105 p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 106 p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 106 107 } 107 108 … … 112 113 //////////// PROCS 113 114 for (size_t p = 0; p < nb_procs; p++) 114 { 115 { 115 116 std::ostringstream s_proc; 116 117 s_proc << "proc_" << x_id << "_" << y_id << "_" << p; … … 120 121 GdbServer<Mips32ElIss> >( 121 122 s_proc.str().c_str(), 122 cluster_id*nb_procs + p,// GLOBAL PROC_ID123 (cluster_id << p_width) + p, // GLOBAL PROC_ID 123 124 mt_int, // Mapping Table INT network 124 125 IntTab(cluster_id,p), // SRCID … … 139 140 } 140 141 141 /////////// MEMC 142 /////////// MEMC 142 143 std::ostringstream s_memc; 143 144 s_memc << "memc_" << x_id << "_" << y_id; … … 204 205 cluster_id, // cluster id 205 206 nb_direct_initiators, // number of local initiators 206 nb_direct_targets, // number of local targets 207 nb_direct_targets, // number of local targets 207 208 0 ); // default target 208 209 … … 234 235 x_width, y_width, l_width, // several dests 235 236 1, // number of local sources 236 nb_procs, // number of local dests 237 2, 2, // fifo depths 237 nb_procs, // number of local dests 238 2, 2, // fifo depths 238 239 true, // pseudo CMD 239 240 false, // no routing table … … 249 250 nb_procs, // number of local sources 250 251 1, // number of local dests 251 2, 2, // fifo depths 252 2, 2, // fifo depths 252 253 false, // pseudo RSP 253 254 false, // no routing table 254 false ); // no broacast 255 false ); // no broacast 255 256 256 257 std::ostringstream s_int_xbar_clack_c; … … 262 263 x_width, y_width, l_width, 263 264 1, // number of local sources 264 nb_procs, // number of local targets 265 nb_procs, // number of local targets 265 266 1, 1, // fifo depths 266 267 true, // CMD … … 330 331 /////////// IO_BRIDGE 331 332 std::ostringstream s_iob; 332 s_iob << "iob_" << x_id << "_" << y_id; 333 s_iob << "iob_" << x_id << "_" << y_id; 333 334 iob = new VciIoBridge<vci_param_int, 334 vci_param_ext>( 335 vci_param_ext>( 335 336 s_iob.str().c_str(), 336 337 mt_ram, // EXT network maptab … … 346 347 debug_start_cycle, 347 348 iob_debug_ok ); 348 349 349 350 std::ostringstream s_iob_ram_wi; 350 s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; 351 s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; 351 352 iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, 352 353 dspin_ram_cmd_width, … … 388 389 // on coherence network : local srcid[proc] in [0...nb_procs-1] 389 390 // : local srcid[memc] = nb_procs 390 391 391 392 //////////////////////// internal CMD & RSP routers 392 393 int_router_cmd->p_clk (this->p_clk); … … 417 418 int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); 418 419 int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); 419 420 420 421 int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); 421 422 int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); … … 453 454 int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); 454 455 int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); 455 456 456 457 ////////////////////// M2P DSPIN local crossbar coherence 457 458 int_xbar_m2p_c->p_clk (this->p_clk); … … 460 461 int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); 461 462 int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); 462 for (size_t p = 0; p < nb_procs; p++) 463 for (size_t p = 0; p < nb_procs; p++) 463 464 int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); 464 465 … … 469 470 int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); 470 471 int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); 471 for (size_t p = 0; p < nb_procs; p++) 472 for (size_t p = 0; p < nb_procs; p++) 472 473 int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); 473 474 … … 511 512 else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); 512 513 else xicu->p_hwi[i] (signal_false); 513 } 514 } 514 515 515 516 ///////////////////////////////////// MEMC … … 576 577 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); 577 578 } 578 579 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 579 580 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 580 581 if ( is_io ) 581 582 {
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