Changeset 802 for trunk/platforms/tsar_generic_iob/non_distributed_arch.py
- Timestamp:
- Sep 12, 2014, 3:10:04 PM (10 years ago)
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- 1 edited
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trunk/platforms/tsar_generic_iob/non_distributed_arch.py
r730 r802 1 1 #!/usr/bin/env python 2 2 3 from math import log, ceil 3 4 from mapping import * 4 5 … … 8 9 # author : Alain Greiner 9 10 ####################################################################################### 10 # This file contains a mapping generator for the "tsar_generic_iob" platform. 11 # This file contains a mapping generator for the "tsar_generic_iob" platform. 11 12 # This includes both the hardware architecture (clusters, processors, peripherals, 12 13 # physical space segmentation) and the mapping of all kernel objects (global vsegs). … … 42 43 43 44 nb_ttys = 1 44 nb_nics = 2 45 nb_nics = 2 45 46 fbf_width = 1024 46 47 x_io = 0 47 48 y_io = 0 49 p_width = int(ceil(log(nb_procs, 2))) 48 50 x_width = 4 49 51 y_width = 4 … … 52 54 use_ramdisk = False 53 55 peri_increment = 0x10000 54 56 55 57 ### parameters checking 56 58 57 assert( nb_procs <= 4)58 59 assert( (x_size == 1) or (x_size == 2) or (x_size == 4) 59 assert( nb_procs <= (1 << p_width) ) 60 61 assert( (x_size == 1) or (x_size == 2) or (x_size == 4) 60 62 or (y_size == 8) or (x_size == 16) ) 61 63 62 assert( (y_size == 1) or (y_size == 2) or (y_size == 4) 64 assert( (y_size == 1) or (y_size == 2) or (y_size == 4) 63 65 or (y_size == 8) or (y_size == 16) ) 64 66 … … 69 71 70 72 platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) 71 73 72 74 ### define physical segments 73 75 … … 75 77 ram_size = 0x4000000 # 64 Mbytes 76 78 77 xcu_base = 0x00B0000000 78 xcu_size = 0x1000 # 4 Kbytes 79 xcu_base = 0x00B0000000 80 xcu_size = 0x1000 # 4 Kbytes 79 81 80 82 dma_base = 0x00B1000000 81 83 dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs 82 84 83 mmc_base = 0x00B2000000 85 mmc_base = 0x00B2000000 84 86 mmc_size = 0x1000 # 4 Kbytes 85 87 … … 116 118 117 119 boot_code_vbase = 0x00010000 # ident 118 boot_code_size = 0x00020000 # 128 Kbytes 119 120 boot_code_size = 0x00020000 # 128 Kbytes 121 120 122 boot_data_vbase = 0x00030000 # ident 121 123 boot_data_size = 0x00010000 # 64 Kbytes … … 129 131 ### define kernel vsegs base addresses 130 132 131 kernel_code_vbase = 0x80000000 133 kernel_code_vbase = 0x80000000 132 134 kernel_code_size = 0x00020000 # 128 Kbytes 133 135 … … 146 148 ### create mapping 147 149 148 mapping = Mapping( name = platform_name, 149 x_size = x_size, 150 y_size = y_size, 151 procs_max = nb_procs, 152 x_width = x_width, 153 y_width = y_width, 154 paddr_width = paddr_width, 155 coherence = True, 156 irq_per_proc = irq_per_proc, 157 use_ramdisk = use_ramdisk, 158 x_io = x_io, 150 mapping = Mapping( name = platform_name, 151 x_size = x_size, 152 y_size = y_size, 153 procs_max = nb_procs, 154 x_width = x_width, 155 y_width = y_width, 156 p_width = p_width, 157 paddr_width = paddr_width, 158 coherence = True, 159 irq_per_proc = irq_per_proc, 160 use_ramdisk = use_ramdisk, 161 x_io = x_io, 159 162 y_io = y_io, 160 peri_increment = peri_increment ) 163 peri_increment = peri_increment ) 161 164 162 165 ### external peripherals (accessible in cluster[0,0] only for this mapping) … … 168 171 tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) 169 172 170 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 173 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 171 174 172 175 cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) … … 193 196 mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 ) 194 197 195 ### hardware components replicated in all clusters 198 ### hardware components replicated in all clusters 196 199 197 200 for x in xrange( x_size ): … … 202 205 ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) 203 206 204 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 207 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 205 208 ptype = 'MMC' ) 206 209 207 dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, 208 ptype = 'DMA', channels = nb_procs ) 209 210 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 210 dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, 211 ptype = 'DMA', channels = nb_procs ) 212 213 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 211 214 ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) 212 215 … … 220 223 ### global vsegs for boot_loader / identity mapping 221 224 222 mapping.addGlobal( 'seg_boot_mapping' , boot_mapping_vbase , boot_mapping_size , 'C_W_', 225 mapping.addGlobal( 'seg_boot_mapping' , boot_mapping_vbase , boot_mapping_size , 'C_W_', 223 226 vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', identity = True ) 224 227 225 mapping.addGlobal( 'seg_boot_code' , boot_code_vbase , boot_code_size , 'CXW_', 228 mapping.addGlobal( 'seg_boot_code' , boot_code_vbase , boot_code_size , 'CXW_', 226 229 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 227 230 228 mapping.addGlobal( 'seg_boot_data' , boot_data_vbase , boot_data_size , 'C_W_', 231 mapping.addGlobal( 'seg_boot_data' , boot_data_vbase , boot_data_size , 'C_W_', 229 232 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 230 233 231 mapping.addGlobal( 'seg_boot_buffer' , boot_buffer_vbase , boot_buffer_size , 'C_W_', 234 mapping.addGlobal( 'seg_boot_buffer' , boot_buffer_vbase , boot_buffer_size , 'C_W_', 232 235 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 233 236 234 mapping.addGlobal( 'seg_boot_stack' , boot_stack_vbase , boot_stack_size , 'C_W_', 237 mapping.addGlobal( 'seg_boot_stack' , boot_stack_vbase , boot_stack_size , 'C_W_', 235 238 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) 236 239 237 ### global vsegs for kernel 238 239 mapping.addGlobal( 'seg_kernel_code' , kernel_code_vbase , kernel_code_size , 'CXW_', 240 ### global vsegs for kernel 241 242 mapping.addGlobal( 'seg_kernel_code' , kernel_code_vbase , kernel_code_size , 'CXW_', 240 243 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 241 244 242 mapping.addGlobal( 'seg_kernel_data' , kernel_data_vbase , kernel_data_size , 'C_W_', 245 mapping.addGlobal( 'seg_kernel_data' , kernel_data_vbase , kernel_data_size , 'C_W_', 243 246 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 244 247 245 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', 248 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', 246 249 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 247 250 248 mapping.addGlobal( 'seg_kernel_init' , kernel_init_vbase , kernel_init_size , 'CXW_', 251 mapping.addGlobal( 'seg_kernel_init' , kernel_init_vbase , kernel_init_size , 'CXW_', 249 252 vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) 250 253 251 254 ### global vsegs for external peripherals / identity mapping 252 255 253 mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 256 mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 254 257 vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', identity = True ) 255 258 256 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 259 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 257 260 vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', identity = True ) 258 261 259 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 262 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 260 263 vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', identity = True ) 261 264 262 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 265 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 263 266 vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', identity = True ) 264 267 265 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 268 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 266 269 vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', identity = True ) 267 270 268 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 271 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 269 272 vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', identity = True ) 270 273 271 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 274 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 272 275 vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True ) 273 276 274 mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', 277 mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', 275 278 vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', identity = True ) 276 279 277 ### Global vsegs for replicated peripherals, and for schedulers 280 ### Global vsegs for replicated peripherals, and for schedulers 278 281 ### name is indexed by (x,y), base address is incremented by (cluster_xy * peri_increment) 279 282 … … 303 306 if __name__ == '__main__': 304 307 305 mapping = genmap( x_size = 2, 306 y_size = 2, 307 nb_procs = 2, 308 nb_ttys = 1, 309 nb_nics = 2, 310 fbf_width = 128, 311 x_io = 0, 312 y_io = 0 ) 308 mapping = arch( x_size = 2, 309 y_size = 2, 310 nb_procs = 2 ) 313 311 314 312 # print mapping.netbsd_dts() … … 317 315 318 316 # print mapping.giet_vsegs() 319 317 320 318 321 319 # Local Variables:
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