- Timestamp:
- Sep 17, 2014, 1:17:56 PM (10 years ago)
- Location:
- branches/reconfiguration/platforms/tsar_generic_iob
- Files:
-
- 1 deleted
- 4 edited
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conf (deleted)
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scripts/arch.py (modified) (4 diffs)
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top.cpp (modified) (35 diffs)
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tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (modified) (15 diffs)
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tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (modified) (22 diffs)
Legend:
- Unmodified
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branches/reconfiguration/platforms/tsar_generic_iob/scripts/arch.py
r774 r806 1 1 #!/usr/bin/env python 2 import sys 2 from math import log 3 3 from mapping import * 4 4 … … 28 28 # - x_width : number of bits for x coordinate 29 29 # - y_width : number of bits for y coordinate 30 # - p_width : number of bits for processor local id field 30 31 # - paddr_width : number of bits for physical address 31 32 # - irq_per_proc : number of input IRQs per processor … … 48 49 x_width = 4 49 50 y_width = 4 51 p_width = log(nb_procs, 2) 50 52 paddr_width = 40 51 53 irq_per_proc = 4 … … 355 357 356 358 ################################# platform test ####################################################### 357 359 import sys 358 360 if __name__ == '__main__': 359 361 main( x_size = int(sys.argv[1]), -
branches/reconfiguration/platforms/tsar_generic_iob/top.cpp
r778 r806 55 55 // - IRQ_IN[4] : DMA channel 3 56 56 // 57 // All clusters are identical, but cluster(0,0) and cluster(X MAX-1,YMAX-1)57 // All clusters are identical, but cluster(0,0) and cluster(X_SIZE-1,Y_SIZE-1) 58 58 // contain an extra IO bridge component. These IOB0 & IOB1 components are 59 59 // connected to the three networks (INT, RAM, IOX). … … 101 101 // All physical segments base addresses are multiple of 1 Mbytes 102 102 // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) 103 // The ( x_width + y_width) MSB bits (left aligned) define103 // The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define 104 104 // the cluster index, and the LADR bits define the local index: 105 105 // |X_ID|Y_ID| LADR | OFFSET | … … 191 191 //////////////////////i///////////////////////////////////// 192 192 193 #define XMAX X_SIZE194 #define YMAX Y_SIZE195 196 193 #define XRAM_LATENCY 0 197 194 … … 237 234 // in the hard_config.h file. For replicated segments, the 238 235 // base address is incremented by a cluster offset: 239 // offset = cluster(x,y) << (address_width- x_width-y_width);236 // offset = cluster(x,y) << (address_width-X_WIDTH-Y_WIDTH); 240 237 241 238 //////////////////////////////////////////////////////////////////////// … … 336 333 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor 337 334 size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 338 size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 339 size_t x_width = 4; // at most 256 clusters 340 size_t y_width = 4; // at most 256 clusters 335 size_t cluster_iob1 = cluster(X_SIZE-1,Y_SIZE-1); // cluster containing IOB1 341 336 342 337 assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and … … 370 365 size_t x = debug_memc_id >> 4; 371 366 size_t y = debug_memc_id & 0xF; 372 if( (x>=X MAX) || (y>=YMAX) )367 if( (x>=X_SIZE) || (y>=Y_SIZE) ) 373 368 { 374 std::cout << "MEMCID parameter does'nt fit X MAX/YMAX" << std::endl;369 std::cout << "MEMCID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; 375 370 exit(0); 376 371 } … … 381 376 size_t x = debug_xram_id >> 4; 382 377 size_t y = debug_xram_id & 0xF; 383 if( (x>=X MAX) || (y>=YMAX) )378 if( (x>=X_SIZE) || (y>=Y_SIZE) ) 384 379 { 385 std::cout << "XRAMID parameter does'nt fit X MAX/YMAX" << std::endl;380 std::cout << "XRAMID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; 386 381 exit(0); 387 382 } … … 397 392 size_t x = cluster_xy >> 4; 398 393 size_t y = cluster_xy & 0xF; 399 if( (x>=X MAX) || (y>=YMAX) )394 if( (x>=X_SIZE) || (y>=Y_SIZE) ) 400 395 { 401 std::cout << "PROCID parameter does'nt fit X MAX/YMAX" << std::endl;396 std::cout << "PROCID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; 402 397 exit(0); 403 398 } … … 446 441 447 442 // checking hardware parameters 448 assert( (X MAX <= 16) and449 "The X MAXparameter cannot be larger than 16" );450 451 assert( (Y MAX <= 16) and452 "The Y MAXparameter cannot be larger than 16" );443 assert( (X_SIZE <= (1 << X_WIDTH)) and 444 "The X_SIZE parameter cannot be larger than 16" ); 445 446 assert( (Y_SIZE <= (1 << Y_WIDTH)) and 447 "The Y_SIZE parameter cannot be larger than 16" ); 453 448 454 449 assert( (NB_PROCS_MAX <= 8) and … … 465 460 466 461 std::cout << std::endl << std::dec 467 << " - X MAX = " << XMAX<< std::endl468 << " - Y MAX = " << YMAX<< std::endl462 << " - X_SIZE = " << X_SIZE << std::endl 463 << " - Y_SIZE = " << Y_SIZE << std::endl 469 464 << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl 470 465 << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl … … 519 514 ///////////////////////////////////////////////////////////////////// 520 515 MappingTable maptab_int( vci_address_width, 521 IntTab( x_width + y_width, 16 - x_width - y_width),522 IntTab( x_width + y_width, vci_srcid_width - x_width - y_width),516 IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), 517 IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), 523 518 0x00FF000000); 524 519 525 for (size_t x = 0; x < X MAX; x++)520 for (size_t x = 0; x < X_SIZE; x++) 526 521 { 527 for (size_t y = 0; y < Y MAX; y++)522 for (size_t y = 0; y < Y_SIZE; y++) 528 523 { 529 524 uint64_t offset = ((uint64_t)cluster(x,y)) 530 << (vci_address_width- x_width-y_width);525 << (vci_address_width-X_WIDTH-Y_WIDTH); 531 526 bool config = true; 532 527 bool cacheable = true; … … 632 627 //////////////////////////////////////////////////////////////////////// 633 628 MappingTable maptab_ram( vci_address_width, 634 IntTab( x_width+y_width, 0),635 IntTab( x_width+y_width, vci_srcid_width - x_width - y_width),629 IntTab(X_WIDTH+Y_WIDTH, 0), 630 IntTab(X_WIDTH+Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), 636 631 0x00FF000000); 637 632 638 for (size_t x = 0; x < X MAX; x++)633 for (size_t x = 0; x < X_SIZE; x++) 639 634 { 640 for (size_t y = 0; y < Y MAX; y++)635 for (size_t y = 0; y < Y_SIZE ; y++) 641 636 { 642 637 uint64_t offset = ((uint64_t)cluster(x,y)) 643 << (vci_address_width- x_width-y_width);638 << (vci_address_width-X_WIDTH-Y_WIDTH); 644 639 645 640 std::ostringstream sxram; … … 692 687 MappingTable maptab_iox( 693 688 vci_address_width, 694 IntTab( x_width + y_width - 1, 16 - x_width - y_width+ 1),695 IntTab( x_width + y_width , vci_param_ext::S - x_width - y_width),689 IntTab(X_WIDTH + Y_WIDTH - 1, 16 - X_WIDTH - Y_WIDTH + 1), 690 IntTab(X_WIDTH + Y_WIDTH , vci_param_ext::S - X_WIDTH - Y_WIDTH), 696 691 0x00FF000000); 697 692 … … 701 696 702 697 const uint64_t iob0_base = ((uint64_t)cluster_iob0) 703 << (vci_address_width - x_width - y_width);698 << (vci_address_width - X_WIDTH - Y_WIDTH); 704 699 705 700 maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TTY_BASE + iob0_base, SEG_TTY_SIZE, … … 721 716 { 722 717 const uint64_t iob1_base = ((uint64_t)cluster_iob1) 723 << (vci_address_width - x_width - y_width);718 << (vci_address_width - X_WIDTH - Y_WIDTH); 724 719 725 720 maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TTY_BASE + iob1_base, SEG_TTY_SIZE, … … 743 738 // As IOMMU is not activated, addresses are 40 bits (physical addresses), 744 739 // and the choice depends on address bit A[32]. 745 for (size_t x = 0; x < X MAX; x++)740 for (size_t x = 0; x < X_SIZE; x++) 746 741 { 747 for (size_t y = 0; y < Y MAX; y++)742 for (size_t y = 0; y < Y_SIZE ; y++) 748 743 { 749 744 const bool wti = true; … … 751 746 752 747 const uint64_t offset = ((uint64_t)cluster(x,y)) 753 << (vci_address_width- x_width-y_width);748 << (vci_address_width-X_WIDTH-Y_WIDTH); 754 749 755 750 const uint64_t xicu_base = SEG_XCU_BASE + offset; … … 835 830 // Horizontal inter-clusters INT network DSPIN 836 831 DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_inc = 837 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", X MAX-1, YMAX, 3);832 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_inc", X_SIZE-1, Y_SIZE, 3); 838 833 DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_h_dec = 839 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", X MAX-1, YMAX, 3);834 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_h_dec", X_SIZE-1, Y_SIZE, 3); 840 835 DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_inc = 841 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", X MAX-1, YMAX, 2);836 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_inc", X_SIZE-1, Y_SIZE, 2); 842 837 DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_h_dec = 843 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", X MAX-1, YMAX, 2);838 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_h_dec", X_SIZE-1, Y_SIZE, 2); 844 839 845 840 // Vertical inter-clusters INT network DSPIN 846 841 DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_inc = 847 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", X MAX, YMAX-1, 3);842 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_inc", X_SIZE, Y_SIZE-1, 3); 848 843 DspinSignals<dspin_int_cmd_width>*** signal_dspin_int_cmd_v_dec = 849 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", X MAX, YMAX-1, 3);844 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_int_cmd_v_dec", X_SIZE, Y_SIZE-1, 3); 850 845 DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_inc = 851 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", X MAX, YMAX-1, 2);846 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_inc", X_SIZE, Y_SIZE-1, 2); 852 847 DspinSignals<dspin_int_rsp_width>*** signal_dspin_int_rsp_v_dec = 853 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", X MAX, YMAX-1, 2);848 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_int_rsp_v_dec", X_SIZE, Y_SIZE-1, 2); 854 849 855 850 // Mesh boundaries INT network DSPIN 856 851 DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_in = 857 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", X MAX, YMAX, 4, 3);852 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_in", X_SIZE, Y_SIZE, 4, 3); 858 853 DspinSignals<dspin_int_cmd_width>**** signal_dspin_false_int_cmd_out = 859 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", X MAX, YMAX, 4, 3);854 alloc_elems<DspinSignals<dspin_int_cmd_width> >("signal_dspin_false_int_cmd_out", X_SIZE, Y_SIZE, 4, 3); 860 855 DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_in = 861 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", X MAX, YMAX, 4, 2);856 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_in", X_SIZE, Y_SIZE, 4, 2); 862 857 DspinSignals<dspin_int_rsp_width>**** signal_dspin_false_int_rsp_out = 863 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", X MAX, YMAX, 4, 2);858 alloc_elems<DspinSignals<dspin_int_rsp_width> >("signal_dspin_false_int_rsp_out", X_SIZE, Y_SIZE, 4, 2); 864 859 865 860 866 861 // Horizontal inter-clusters RAM network DSPIN 867 862 DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_inc = 868 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", X MAX-1, YMAX);863 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_inc", X_SIZE-1, Y_SIZE); 869 864 DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_h_dec = 870 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", X MAX-1, YMAX);865 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_h_dec", X_SIZE-1, Y_SIZE); 871 866 DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_inc = 872 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", X MAX-1, YMAX);867 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_inc", X_SIZE-1, Y_SIZE); 873 868 DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_h_dec = 874 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", X MAX-1, YMAX);869 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_h_dec", X_SIZE-1, Y_SIZE); 875 870 876 871 // Vertical inter-clusters RAM network DSPIN 877 872 DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_inc = 878 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", X MAX, YMAX-1);873 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_inc", X_SIZE, Y_SIZE-1); 879 874 DspinSignals<dspin_ram_cmd_width>** signal_dspin_ram_cmd_v_dec = 880 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", X MAX, YMAX-1);875 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_ram_cmd_v_dec", X_SIZE, Y_SIZE-1); 881 876 DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_inc = 882 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", X MAX, YMAX-1);877 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_inc", X_SIZE, Y_SIZE-1); 883 878 DspinSignals<dspin_ram_rsp_width>** signal_dspin_ram_rsp_v_dec = 884 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", X MAX, YMAX-1);879 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_ram_rsp_v_dec", X_SIZE, Y_SIZE-1); 885 880 886 881 // Mesh boundaries RAM network DSPIN 887 882 DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_in = 888 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", X MAX, YMAX, 4);883 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_in", X_SIZE, Y_SIZE, 4); 889 884 DspinSignals<dspin_ram_cmd_width>*** signal_dspin_false_ram_cmd_out = 890 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", X MAX, YMAX, 4);885 alloc_elems<DspinSignals<dspin_ram_cmd_width> >("signal_dspin_false_ram_cmd_out", X_SIZE, Y_SIZE, 4); 891 886 DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_in = 892 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", X MAX, YMAX, 4);887 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_in", X_SIZE, Y_SIZE, 4); 893 888 DspinSignals<dspin_ram_rsp_width>*** signal_dspin_false_ram_rsp_out = 894 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", X MAX, YMAX, 4);889 alloc_elems<DspinSignals<dspin_ram_rsp_width> >("signal_dspin_false_ram_rsp_out", X_SIZE, Y_SIZE, 4); 895 890 896 891 //////////////////////////// … … 1003 998 dspin_int_rsp_width, 1004 999 dspin_ram_cmd_width, 1005 dspin_ram_rsp_width>* clusters[X MAX][YMAX];1000 dspin_ram_rsp_width>* clusters[X_SIZE][Y_SIZE]; 1006 1001 1007 1002 #if USE_OPENMP … … 1010 1005 #pragma omp for 1011 1006 #endif 1012 for(size_t i = 0; i < (X MAX * YMAX); i++)1007 for(size_t i = 0; i < (X_SIZE * Y_SIZE); i++) 1013 1008 { 1014 size_t x = i / Y MAX;1015 size_t y = i % Y MAX;1009 size_t x = i / Y_SIZE; 1010 size_t y = i % Y_SIZE; 1016 1011 1017 1012 #if USE_OPENMP … … 1048 1043 x, 1049 1044 y, 1050 XMAX, 1051 YMAX, 1045 X_SIZE, 1046 Y_SIZE, 1047 1048 P_WIDTH, 1052 1049 1053 1050 maptab_int, … … 1055 1052 maptab_iox, 1056 1053 1057 x_width,1058 y_width,1059 vci_srcid_width - x_width - y_width, // l_id width,1054 X_WIDTH, 1055 Y_WIDTH, 1056 vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width, 1060 1057 1061 1058 INT_MEMC_TGT_ID, … … 1216 1213 if ( cluster_iob0 != cluster_iob1 ) 1217 1214 { 1218 (*clusters[X MAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1);1219 (*clusters[X MAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1);1215 (*clusters[X_SIZE-1][Y_SIZE-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); 1216 (*clusters[X_SIZE-1][Y_SIZE-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); 1220 1217 } 1221 1218 1222 1219 // All clusters Clock & RESET connexions 1223 for ( size_t x = 0; x < (X MAX); x++ )1220 for ( size_t x = 0; x < (X_SIZE); x++ ) 1224 1221 { 1225 for (size_t y = 0; y < Y MAX; y++)1222 for (size_t y = 0; y < Y_SIZE; y++) 1226 1223 { 1227 1224 clusters[x][y]->p_clk (signal_clk); … … 1231 1228 1232 1229 // Inter Clusters horizontal connections 1233 if (X MAX> 1)1230 if (X_SIZE > 1) 1234 1231 { 1235 for (size_t x = 0; x < (X MAX-1); x++)1232 for (size_t x = 0; x < (X_SIZE-1); x++) 1236 1233 { 1237 for (size_t y = 0; y < Y MAX; y++)1234 for (size_t y = 0; y < Y_SIZE; y++) 1238 1235 { 1239 1236 for (size_t k = 0; k < 3; k++) … … 1268 1265 1269 1266 // Inter Clusters vertical connections 1270 if (Y MAX> 1)1267 if (Y_SIZE > 1) 1271 1268 { 1272 for (size_t y = 0; y < (Y MAX-1); y++)1269 for (size_t y = 0; y < (Y_SIZE-1); y++) 1273 1270 { 1274 for (size_t x = 0; x < X MAX; x++)1271 for (size_t x = 0; x < X_SIZE; x++) 1275 1272 { 1276 1273 for (size_t k = 0; k < 3; k++) … … 1305 1302 1306 1303 // East & West boundary cluster connections 1307 for (size_t y = 0; y < Y MAX; y++)1304 for (size_t y = 0; y < Y_SIZE; y++) 1308 1305 { 1309 1306 for (size_t k = 0; k < 3; k++) … … 1311 1308 clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); 1312 1309 clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); 1313 clusters[X MAX-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST][k]);1314 clusters[X MAX-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST][k]);1310 clusters[X_SIZE-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[X_SIZE-1][y][EAST][k]); 1311 clusters[X_SIZE-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[X_SIZE-1][y][EAST][k]); 1315 1312 } 1316 1313 … … 1319 1316 clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); 1320 1317 clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); 1321 clusters[X MAX-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST][k]);1322 clusters[X MAX-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST][k]);1318 clusters[X_SIZE-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[X_SIZE-1][y][EAST][k]); 1319 clusters[X_SIZE-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[X_SIZE-1][y][EAST][k]); 1323 1320 } 1324 1321 … … 1328 1325 clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); 1329 1326 1330 clusters[X MAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]);1331 clusters[X MAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]);1332 clusters[X MAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]);1333 clusters[X MAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]);1327 clusters[X_SIZE-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[X_SIZE-1][y][EAST]); 1328 clusters[X_SIZE-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[X_SIZE-1][y][EAST]); 1329 clusters[X_SIZE-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[X_SIZE-1][y][EAST]); 1330 clusters[X_SIZE-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[X_SIZE-1][y][EAST]); 1334 1331 } 1335 1332 … … 1337 1334 1338 1335 // North & South boundary clusters connections 1339 for (size_t x = 0; x < X MAX; x++)1336 for (size_t x = 0; x < X_SIZE; x++) 1340 1337 { 1341 1338 for (size_t k = 0; k < 3; k++) … … 1343 1340 clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); 1344 1341 clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); 1345 clusters[x][Y MAX-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH][k]);1346 clusters[x][Y MAX-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH][k]);1342 clusters[x][Y_SIZE-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][Y_SIZE-1][NORTH][k]); 1343 clusters[x][Y_SIZE-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][Y_SIZE-1][NORTH][k]); 1347 1344 } 1348 1345 … … 1351 1348 clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); 1352 1349 clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); 1353 clusters[x][Y MAX-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH][k]);1354 clusters[x][Y MAX-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH][k]);1350 clusters[x][Y_SIZE-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][Y_SIZE-1][NORTH][k]); 1351 clusters[x][Y_SIZE-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][Y_SIZE-1][NORTH][k]); 1355 1352 } 1356 1353 … … 1360 1357 clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); 1361 1358 1362 clusters[x][Y MAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]);1363 clusters[x][Y MAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]);1364 clusters[x][Y MAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]);1365 clusters[x][Y MAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]);1359 clusters[x][Y_SIZE-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][Y_SIZE-1][NORTH]); 1360 clusters[x][Y_SIZE-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][Y_SIZE-1][NORTH]); 1361 clusters[x][Y_SIZE-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][Y_SIZE-1][NORTH]); 1362 clusters[x][Y_SIZE-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][Y_SIZE-1][NORTH]); 1366 1363 } 1367 1364 … … 1378 1375 1379 1376 // network boundaries signals 1380 for (size_t x = 0; x < X MAX; x++)1377 for (size_t x = 0; x < X_SIZE ; x++) 1381 1378 { 1382 for (size_t y = 0; y < Y MAX; y++)1379 for (size_t y = 0; y < Y_SIZE ; y++) 1383 1380 { 1384 1381 for (size_t a = 0; a < 4; a++) … … 1525 1522 { 1526 1523 clusters[0][0]->iob->print_trace(); 1527 clusters[X MAX-1][YMAX-1]->iob->print_trace();1524 clusters[X_SIZE-1][Y_SIZE-1]->iob->print_trace(); 1528 1525 // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); 1529 1526 // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); -
branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r748 r806 1 1 ////////////////////////////////////////////////////////////////////////////// 2 2 // File: tsar_iob_cluster.h 3 // Author: Alain Greiner 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 5 // Date : april 2013 … … 37 37 38 38 /////////////////////////////////////////////////////////////////////////// 39 template<typename vci_param_int, 39 template<typename vci_param_int, 40 40 typename vci_param_ext, 41 size_t dspin_int_cmd_width, 41 size_t dspin_int_cmd_width, 42 42 size_t dspin_int_rsp_width, 43 43 size_t dspin_ram_cmd_width, 44 44 size_t dspin_ram_rsp_width> 45 class TsarIobCluster 45 class TsarIobCluster 46 46 /////////////////////////////////////////////////////////////////////////// 47 47 : public soclib::caba::BaseModule … … 56 56 // Thes two ports are used to connect IOB to IOX nework in top cell 57 57 soclib::caba::VciInitiator<vci_param_ext>* p_vci_iob_iox_ini; 58 soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; 58 soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; 59 59 60 60 // These arrays of ports are used to connect the INT & RAM networks in top cell … … 74 74 sc_signal<bool> signal_irq_mdma[8]; 75 75 sc_signal<bool> signal_irq_memc; 76 76 77 77 // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars 78 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 79 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 78 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_l2g_d; 79 DspinSignals<dspin_int_cmd_width> signal_int_dspin_cmd_g2l_d; 80 80 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_l2g_c; 81 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 81 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_g2l_c; 82 82 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_l2g_c; 83 83 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_g2l_c; 84 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 85 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 84 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_l2g_d; 85 DspinSignals<dspin_int_rsp_width> signal_int_dspin_rsp_g2l_d; 86 86 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_l2g_c; 87 87 DspinSignals<dspin_int_rsp_width> signal_int_dspin_p2m_g2l_c; 88 88 89 89 // INT network VCI signals between VCI components and VCI local crossbar 90 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 91 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 92 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 90 VciSignals<vci_param_int> signal_int_vci_ini_proc[8]; 91 VciSignals<vci_param_int> signal_int_vci_ini_mdma; 92 VciSignals<vci_param_int> signal_int_vci_ini_iobx; 93 93 94 94 VciSignals<vci_param_int> signal_int_vci_tgt_memc; … … 101 101 VciSignals<vci_param_int> signal_int_vci_g2l; 102 102 103 // Coherence DSPIN signals between DSPIN local crossbars and CC components 103 // Coherence DSPIN signals between DSPIN local crossbars and CC components 104 104 DspinSignals<dspin_int_cmd_width> signal_int_dspin_m2p_memc; 105 105 DspinSignals<dspin_int_cmd_width> signal_int_dspin_clack_memc; … … 115 115 116 116 // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar 117 // and routers 117 // and routers 118 118 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; 119 119 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; … … 126 126 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false; 127 127 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false; 128 128 129 129 ////////////////////////////////////// 130 130 // Hardwate Components (pointers) 131 131 ////////////////////////////////////// 132 VciCcVCacheWrapper<vci_param_int, 132 VciCcVCacheWrapper<vci_param_int, 133 133 dspin_int_cmd_width, 134 134 dspin_int_rsp_width, … … 136 136 137 137 VciMemCache<vci_param_int, 138 vci_param_ext, 139 dspin_int_rsp_width, 138 vci_param_ext, 139 dspin_int_rsp_width, 140 140 dspin_int_cmd_width>* memc; 141 141 … … 151 151 152 152 VciLocalCrossbar<vci_param_int>* int_xbar_d; 153 153 154 154 VciDspinInitiatorWrapper<vci_param_int, 155 155 dspin_int_cmd_width, … … 172 172 dspin_ram_cmd_width, 173 173 dspin_ram_rsp_width>* xram_ram_wt; 174 174 175 175 DspinRouter<dspin_ram_cmd_width>* ram_router_cmd; 176 176 DspinRouter<dspin_ram_rsp_width>* ram_router_rsp; … … 178 178 DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd; 179 179 DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp; 180 180 181 181 182 182 // IO Network Components (not instanciated in all clusters) … … 191 191 // cluster constructor 192 192 TsarIobCluster( sc_module_name insname, 193 size_t nb_procs, 194 size_t nb_dmas, 193 size_t nb_procs, 194 size_t nb_dmas, 195 195 size_t x, // x coordinate 196 196 size_t y, // y coordinate 197 size_t xmax, 198 size_t ymax, 197 size_t x_size, 198 size_t y_size, 199 200 size_t p_width, // pid field bits 199 201 200 202 const soclib::common::MappingTable &mt_int, … … 226 228 size_t memc_sets, 227 229 size_t l1_i_ways, 228 size_t l1_i_sets, 230 size_t l1_i_sets, 229 231 size_t l1_d_ways, 230 size_t l1_d_sets, 231 size_t xram_latency, 232 size_t l1_d_sets, 233 size_t xram_latency, 232 234 size_t xcu_nb_inputs, 233 235 … … 236 238 const Loader &loader, // loader for XRAM 237 239 238 uint32_t frozen_cycles, 240 uint32_t frozen_cycles, 239 241 uint32_t start_debug_cycle, 240 bool memc_debug_ok, 241 bool proc_debug_ok, 242 bool iob0_debug_ok ); 242 bool memc_debug_ok, 243 bool proc_debug_ok, 244 bool iob0_debug_ok ); 243 245 244 246 protected: … … 247 249 248 250 void init(); 249 251 250 252 251 253 }; -
branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r748 r806 1 1 ////////////////////////////////////////////////////////////////////////////// 2 2 // File: tsar_iob_cluster.cpp 3 // Author: Alain Greiner 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 5 // Date : april 2013 6 6 // This program is released under the GNU public license 7 7 ////////////////////////////////////////////////////////////////////////////// 8 // Cluster(0,0) & Cluster(x max-1,ymax-1) contains the IOB0 & IOB1 components.8 // Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components. 9 9 // These two clusters contain 6 extra components: 10 10 // - 1 vci_io_bridge (connected to the 3 networks. 11 11 // - 3 vci_dspin_wrapper for the IOB. 12 // - 2 dspin_local_crossbar for commands and responses. 12 // - 2 dspin_local_crossbar for commands and responses. 13 13 ////////////////////////////////////////////////////////////////////////////// 14 14 … … 30 30 ////////////////////////////////////////////////////////////////////////// 31 31 tmpl(/**/)::TsarIobCluster( 32 ////////////////////////////////////////////////////////////////////////// 33 sc_module_name insname, 34 size_t nb_procs, 35 size_t nb_dmas, 36 size_t x_id, 37 size_t y_id, 38 size_t xmax, 39 size_t ymax, 40 41 const soclib::common::MappingTable &mt_int, 42 const soclib::common::MappingTable &mt_ram, 43 const soclib::common::MappingTable &mt_iox, 44 45 size_t x_width, 46 size_t y_width, 47 size_t l_width, 48 49 size_t int_memc_tgt_id, // local index 50 size_t int_xicu_tgt_id, // local index 51 size_t int_mdma_tgt_id, // local index 52 size_t int_brom_tgt_id, // local index 53 size_t int_iobx_tgt_id, // local index 54 55 size_t int_proc_ini_id, // local index 56 size_t int_mdma_ini_id, // local index 57 size_t int_iobx_ini_id, // local index 58 59 size_t ram_xram_tgt_id, // local index 60 size_t ram_memc_ini_id, // local index 61 size_t ram_iobx_ini_id, // local index 62 63 bool is_io, // is IO cluster (IOB)? 64 size_t iox_iobx_tgt_id, // local_index 65 size_t iox_iobx_ini_id, // local index 66 67 size_t memc_ways, 68 size_t memc_sets, 69 size_t l1_i_ways, 70 size_t l1_i_sets, 71 size_t l1_d_ways, 72 size_t l1_d_sets, 73 size_t xram_latency, 74 size_t xcu_nb_inputs, 75 76 bool distboot, 77 78 const Loader &loader, 79 80 uint32_t frozen_cycles, 81 uint32_t debug_start_cycle, 82 bool memc_debug_ok, 83 bool proc_debug_ok, 84 bool iob_debug_ok ) 85 : soclib::caba::BaseModule(insname), 86 p_clk("clk"), 87 p_resetn("resetn") 32 sc_module_name insname, 33 size_t nb_procs, 34 size_t nb_dmas, 35 size_t x_id, 36 size_t y_id, 37 size_t x_size, 38 size_t y_size, 39 40 size_t p_width, 41 42 const soclib::common::MappingTable &mt_int, 43 const soclib::common::MappingTable &mt_ram, 44 const soclib::common::MappingTable &mt_iox, 45 46 size_t x_width, 47 size_t y_width, 48 size_t l_width, 49 50 size_t int_memc_tgt_id, // local index 51 size_t int_xicu_tgt_id, // local index 52 size_t int_mdma_tgt_id, // local index 53 size_t int_brom_tgt_id, // local index 54 size_t int_iobx_tgt_id, // local index 55 56 size_t int_proc_ini_id, // local index 57 size_t int_mdma_ini_id, // local index 58 size_t int_iobx_ini_id, // local index 59 60 size_t ram_xram_tgt_id, // local index 61 size_t ram_memc_ini_id, // local index 62 size_t ram_iobx_ini_id, // local index 63 64 bool is_io, // is IO cluster (IOB)? 65 size_t iox_iobx_tgt_id, // local_index 66 size_t iox_iobx_ini_id, // local index 67 68 size_t memc_ways, 69 size_t memc_sets, 70 size_t l1_i_ways, 71 size_t l1_i_sets, 72 size_t l1_d_ways, 73 size_t l1_d_sets, 74 size_t xram_latency, 75 size_t xcu_nb_inputs, 76 77 bool distboot, 78 79 const Loader &loader, 80 81 uint32_t frozen_cycles, 82 uint32_t debug_start_cycle, 83 bool memc_debug_ok, 84 bool proc_debug_ok, 85 bool iob_debug_ok ) : 86 87 // constructor initialization list 88 89 soclib::caba::BaseModule(insname), 90 p_clk("clk"), 91 p_resetn("resetn") 88 92 { 89 assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); 90 91 size_t cluster_id = (x_id<<4) + y_id; 93 94 assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates"); 95 96 size_t cluster_id = (x_id << x_width) | y_id; 92 97 93 98 // Vectors of DSPIN ports for inter-cluster communications … … 103 108 104 109 // VCI ports from IOB to IOX network (only in IO clusters) 105 if ( is_io)110 if (is_io) 106 111 { 107 112 p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; 108 p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 113 p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 109 114 } 110 115 … … 115 120 //////////// PROCS 116 121 for (size_t p = 0; p < nb_procs; p++) 117 { 122 { 118 123 std::ostringstream s_proc; 119 124 s_proc << "proc_" << x_id << "_" << y_id << "_" << p; … … 123 128 GdbServer<Mips32ElIss> >( 124 129 s_proc.str().c_str(), 125 cluster_id*nb_procs + p,// GLOBAL PROC_ID130 (cluster_id << p_width) | p, // GLOBAL PROC_ID 126 131 mt_int, // Mapping Table INT network 127 132 IntTab(cluster_id,p), // SRCID 128 (cluster_id << l_width) +p, // CC_GLOBAL_ID133 (cluster_id << l_width) | p, // CC_GLOBAL_ID 129 134 8, // ITLB ways 130 135 8, // ITLB sets … … 135 140 4, // WBUF nlines 136 141 4, // WBUF nwords 137 x_width, 138 y_width, 142 x_width, // number of bits for x coordinate 143 y_width, // number of bits for y coordinate 139 144 frozen_cycles, // max frozen cycles 140 145 debug_start_cycle, … … 150 155 } 151 156 152 /////////// MEMC 157 /////////// MEMC 153 158 std::ostringstream s_memc; 154 159 s_memc << "memc_" << x_id << "_" << y_id; … … 225 230 cluster_id, // cluster id 226 231 nb_direct_initiators, // number of local initiators 227 nb_direct_targets, // number of local targets 232 nb_direct_targets, // number of local targets 228 233 0 ); // default target 229 234 … … 255 260 x_width, y_width, l_width, // several dests 256 261 1, // number of local sources 257 nb_procs, // number of local dests 258 2, 2, // fifo depths 262 nb_procs, // number of local dests 263 2, 2, // fifo depths 259 264 true, // pseudo CMD 260 265 false, // no routing table … … 270 275 nb_procs, // number of local sources 271 276 1, // number of local dests 272 2, 2, // fifo depths 277 2, 2, // fifo depths 273 278 false, // pseudo RSP 274 279 false, // no routing table 275 false ); // no broacast 280 false ); // no broacast 276 281 277 282 std::ostringstream s_int_xbar_clack_c; … … 283 288 x_width, y_width, l_width, 284 289 1, // number of local sources 285 nb_procs, // number of local targets 290 nb_procs, // number of local targets 286 291 1, 1, // fifo depths 287 292 true, // CMD … … 297 302 x_width, y_width, // x & y fields width 298 303 3, // nb virtual channels 299 4, 4);// input & output fifo depths304 4, 4); // input & output fifo depths 300 305 301 306 std::ostringstream s_int_router_rsp; … … 306 311 x_width, y_width, // x & y fields width 307 312 2, // nb virtual channels 308 4, 4);// input & output fifo depths313 4, 4); // input & output fifo depths 309 314 310 315 ////////////// XRAM … … 351 356 /////////// IO_BRIDGE 352 357 std::ostringstream s_iob; 353 s_iob << "iob_" << x_id << "_" << y_id; 358 s_iob << "iob_" << x_id << "_" << y_id; 354 359 iob = new VciIoBridge<vci_param_int, 355 vci_param_ext>( 360 vci_param_ext>( 356 361 s_iob.str().c_str(), 357 362 mt_ram, // EXT network maptab … … 367 372 debug_start_cycle, 368 373 iob_debug_ok ); 369 374 370 375 std::ostringstream s_iob_ram_wi; 371 s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; 376 s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; 372 377 iob_ram_wi = new VciDspinInitiatorWrapper<vci_param_ext, 373 378 dspin_ram_cmd_width, … … 409 414 // on coherence network : local srcid[proc] in [0...nb_procs-1] 410 415 // : local srcid[memc] = nb_procs 411 416 412 417 //////////////////////// internal CMD & RSP routers 413 418 int_router_cmd->p_clk (this->p_clk); … … 438 443 int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); 439 444 int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); 440 445 441 446 int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); 442 447 int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); … … 475 480 int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); 476 481 int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); 477 482 478 483 ////////////////////// M2P DSPIN local crossbar coherence 479 484 int_xbar_m2p_c->p_clk (this->p_clk); … … 482 487 int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); 483 488 int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); 484 for (size_t p = 0; p < nb_procs; p++) 489 for (size_t p = 0; p < nb_procs; p++) 485 490 int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); 486 491 … … 491 496 int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); 492 497 int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); 493 for (size_t p = 0; p < nb_procs; p++) 498 for (size_t p = 0; p < nb_procs; p++) 494 499 int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); 495 500 … … 533 538 else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); 534 539 else xicu->p_hwi[i] (signal_false); 535 } 540 } 536 541 537 542 ///////////////////////////////////// MEMC … … 603 608 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); 604 609 } 605 606 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 610 611 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 607 612 if ( is_io ) 608 613 {
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