- Timestamp:
- Sep 30, 2014, 4:53:01 PM (10 years ago)
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branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r805 r824 56 56 57 57 //////////////////////////////////////////// 58 template<typename vci_param, 58 template<typename vci_param, 59 59 size_t dspin_in_width, 60 60 size_t dspin_out_width, … … 67 67 typedef typename vci_param::fast_addr_t paddr_t; 68 68 69 enum icache_fsm_state_e 69 enum icache_fsm_state_e 70 70 { 71 71 ICACHE_IDLE, … … 94 94 }; 95 95 96 enum dcache_fsm_state_e 96 enum dcache_fsm_state_e 97 97 { 98 98 DCACHE_IDLE, … … 108 108 DCACHE_TLB_LR_WAIT, 109 109 DCACHE_TLB_RETURN, 110 110 // handling processor XTN requests 111 111 DCACHE_XTN_SWITCH, 112 112 DCACHE_XTN_SYNC, … … 128 128 DCACHE_DIRTY_GET_PTE, 129 129 DCACHE_DIRTY_WAIT, 130 130 // handling processor miss requests 131 131 DCACHE_MISS_SELECT, 132 132 DCACHE_MISS_CLEAN, … … 148 148 }; 149 149 150 enum cmd_fsm_state_e 150 enum cmd_fsm_state_e 151 151 { 152 152 CMD_IDLE, … … 162 162 }; 163 163 164 enum rsp_fsm_state_e 164 enum rsp_fsm_state_e 165 165 { 166 166 RSP_IDLE, … … 173 173 }; 174 174 175 enum cc_receive_fsm_state_e 175 enum cc_receive_fsm_state_e 176 176 { 177 177 CC_RECEIVE_IDLE, … … 190 190 }; 191 191 192 enum cc_send_fsm_state_e 192 enum cc_send_fsm_state_e 193 193 { 194 194 CC_SEND_IDLE, … … 228 228 229 229 // cc_send_type 230 typedef enum 230 typedef enum 231 231 { 232 232 CC_TYPE_CLEANUP, … … 235 235 236 236 // cc_receive_type 237 typedef enum 237 typedef enum 238 238 { 239 239 CC_TYPE_CLACK, … … 244 244 245 245 // TLB Mode : ITLB / DTLB / ICACHE / DCACHE 246 enum 246 enum 247 247 { 248 248 INS_TLB_MASK = 0x8, … … 256 256 { 257 257 MMU_NONE = 0x0000, // None 258 MMU_WRITE_PT1_UNMAPPED 259 MMU_WRITE_PT2_UNMAPPED 258 MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write & Page fault on PT1 259 MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write & Page fault on PT2 260 260 MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode 261 261 MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write to non writable page … … 264 264 MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write & Bus Error accessing PT2 265 265 MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access 266 MMU_READ_PT1_UNMAPPED 267 MMU_READ_PT2_UNMAPPED 266 MMU_READ_PT1_UNMAPPED = 0x1001, // Read & Page fault on PT1 267 MMU_READ_PT2_UNMAPPED = 0x1002, // Read & Page fault on PT2 268 268 MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read & Protected access in user mode 269 269 MMU_READ_EXEC_VIOLATION = 0x1010, // Read & Exec access to a non exec page 270 MMU_READ_UNDEFINED_XTN 270 MMU_READ_UNDEFINED_XTN = 0x1020, // Read & Undefined external access 271 271 MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read & Bus Error accessing PT1 272 272 MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 … … 310 310 const size_t m_cc_global_id; 311 311 const size_t m_nline_width; 312 const size_t 313 const size_t 314 const size_t 315 const size_t 316 const size_t 317 const size_t 318 const paddr_t 319 const size_t 320 const size_t 321 const size_t 322 const paddr_t 323 const size_t 312 const size_t m_itlb_ways; 313 const size_t m_itlb_sets; 314 const size_t m_dtlb_ways; 315 const size_t m_dtlb_sets; 316 const size_t m_icache_ways; 317 const size_t m_icache_sets; 318 const paddr_t m_icache_yzmask; 319 const size_t m_icache_words; 320 const size_t m_dcache_ways; 321 const size_t m_dcache_sets; 322 const paddr_t m_dcache_yzmask; 323 const size_t m_dcache_words; 324 324 const size_t m_x_width; 325 325 const size_t m_y_width; 326 326 const size_t m_proc_id; 327 const uint32_t 328 const size_t 327 const uint32_t m_max_frozen_cycles; 328 const size_t m_paddr_nbits; 329 329 uint32_t m_debug_start_cycle; 330 330 bool m_debug_ok; … … 342 342 343 343 ///////////////////////////////////////////// 344 // debug variables 344 // debug variables 345 345 ///////////////////////////////////////////// 346 346 bool m_debug_previous_i_hit; … … 351 351 // Software visible REGISTERS 352 352 /////////////////////////////// 353 sc_signal<uint32_t> r_mmu_ptpr; 354 sc_signal<uint32_t> r_mmu_mode; 355 sc_signal<uint32_t> r_mmu_word_lo; 356 sc_signal<uint32_t> r_mmu_word_hi; 357 sc_signal<uint32_t> r_mmu_ibvar; 358 sc_signal<uint32_t> r_mmu_dbvar; 359 sc_signal<uint32_t> r_mmu_ietr; 360 sc_signal<uint32_t> r_mmu_detr; 361 uint32_t r_mmu_params;// read-only362 uint32_t r_mmu_release;// read_only353 sc_signal<uint32_t> r_mmu_ptpr; // page table pointer register 354 sc_signal<uint32_t> r_mmu_mode; // mmu mode register 355 sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low 356 sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight 357 sc_signal<uint32_t> r_mmu_ibvar; // mmu bad instruction address 358 sc_signal<uint32_t> r_mmu_dbvar; // mmu bad data address 359 sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type 360 sc_signal<uint32_t> r_mmu_detr; // mmu data error type 361 uint32_t r_mmu_params; // read-only 362 uint32_t r_mmu_release; // read_only 363 363 364 364 … … 368 368 sc_signal<int> r_icache_fsm; // state register 369 369 sc_signal<int> r_icache_fsm_save; // return state for coherence op 370 sc_signal<paddr_t> r_icache_vci_paddr; 370 sc_signal<paddr_t> r_icache_vci_paddr; // physical address 371 371 sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor 372 372 373 373 // icache miss handling 374 sc_signal<size_t> r_icache_miss_way; 375 sc_signal<size_t> r_icache_miss_set; 376 sc_signal<size_t> r_icache_miss_word; 374 sc_signal<size_t> r_icache_miss_way; // selected way for cache update 375 sc_signal<size_t> r_icache_miss_set; // selected set for cache update 376 sc_signal<size_t> r_icache_miss_word; // word index ( cache update) 377 377 sc_signal<bool> r_icache_miss_inval; // coherence request matching a miss 378 378 sc_signal<bool> r_icache_miss_clack; // waiting for a cleanup acknowledge 379 379 380 380 // coherence request handling 381 sc_signal<size_t> r_icache_cc_way; 382 sc_signal<size_t> r_icache_cc_set; 383 sc_signal<size_t> r_icache_cc_word; 381 sc_signal<size_t> r_icache_cc_way; // selected way for cc update/inval 382 sc_signal<size_t> r_icache_cc_set; // selected set for cc update/inval 383 sc_signal<size_t> r_icache_cc_word; // word counter for cc update 384 384 sc_signal<bool> r_icache_cc_need_write; // activate the cache for writing 385 385 386 386 // coherence clack handling 387 387 sc_signal<bool> r_icache_clack_req; // clack request 388 sc_signal<size_t> r_icache_clack_way; 389 sc_signal<size_t> r_icache_clack_set; 388 sc_signal<size_t> r_icache_clack_way; // clack way 389 sc_signal<size_t> r_icache_clack_set; // clack set 390 390 391 391 // icache flush handling 392 sc_signal<size_t> r_icache_flush_count; 392 sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush 393 393 394 394 // communication between ICACHE FSM and VCI_CMD FSM … … 397 397 398 398 // communication between ICACHE FSM and DCACHE FSM 399 sc_signal<bool> 399 sc_signal<bool> r_icache_tlb_miss_req; // (set icache/reset dcache) 400 400 sc_signal<bool> r_icache_tlb_rsp_error; // tlb miss response error 401 401 402 402 // Flip-Flop in ICACHE FSM for saving the cleanup victim request 403 sc_signal<bool> r_icache_cleanup_victim_req; 403 sc_signal<bool> r_icache_cleanup_victim_req; 404 404 sc_signal<paddr_t> r_icache_cleanup_victim_nline; 405 405 … … 427 427 sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) 428 428 sc_signal<paddr_t> r_dcache_save_paddr; // physical address 429 sc_signal<size_t> r_dcache_save_cache_way; 430 sc_signal<size_t> r_dcache_save_cache_set; 431 sc_signal<size_t> r_dcache_save_cache_word; 429 sc_signal<size_t> r_dcache_save_cache_way; // selected way (from dcache) 430 sc_signal<size_t> r_dcache_save_cache_set; // selected set (from dcache) 431 sc_signal<size_t> r_dcache_save_cache_word; // selected word (from dcache) 432 432 // registers used by the Dirty bit sub-fsm 433 433 sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address 434 sc_signal<size_t> r_dcache_dirty_way; 435 sc_signal<size_t> r_dcache_dirty_set; 434 sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache 435 sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache 436 436 437 437 // communication between DCACHE FSM and VCI_CMD FSM 438 sc_signal<paddr_t> r_dcache_vci_paddr; 439 sc_signal<uint32_t> r_dcache_vci_wdata; 438 sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command 439 sc_signal<uint32_t> r_dcache_vci_wdata; // write unc data for VCI command 440 440 sc_signal<bool> r_dcache_vci_miss_req; // read miss request 441 441 sc_signal<bool> r_dcache_vci_unc_req; // uncacheable request (read/write) … … 456 456 457 457 // register used for XTN inval 458 sc_signal<size_t> r_dcache_xtn_way; 459 sc_signal<size_t> r_dcache_xtn_set; 458 sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) 459 sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) 460 460 461 461 // handling dcache miss 462 sc_signal<int> r_dcache_miss_type;// depending on the requester463 sc_signal<size_t> r_dcache_miss_word; 464 sc_signal<size_t> r_dcache_miss_way; 465 sc_signal<size_t> r_dcache_miss_set; 462 sc_signal<int> r_dcache_miss_type; // depending on the requester 463 sc_signal<size_t> r_dcache_miss_word; // word index for cache update 464 sc_signal<size_t> r_dcache_miss_way; // selected way for cache update 465 sc_signal<size_t> r_dcache_miss_set; // selected set for cache update 466 466 sc_signal<bool> r_dcache_miss_inval; // coherence request matching a miss 467 467 sc_signal<bool> r_dcache_miss_clack; // waiting for a cleanup acknowledge 468 468 469 469 // handling coherence requests 470 sc_signal<size_t> r_dcache_cc_way; 471 sc_signal<size_t> r_dcache_cc_set; 470 sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval 471 sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval 472 472 sc_signal<int> r_dcache_cc_state; // state of selected cache slot 473 sc_signal<size_t> r_dcache_cc_word; 473 sc_signal<size_t> r_dcache_cc_word; // word counter for cc update 474 474 sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing 475 475 sc_signal<paddr_t> r_dcache_cc_inval_addr; // address for a cleanup transaction … … 478 478 // coherence clack handling 479 479 sc_signal<bool> r_dcache_clack_req; // clack request 480 sc_signal<size_t> r_dcache_clack_way; 481 sc_signal<size_t> r_dcache_clack_set; 480 sc_signal<size_t> r_dcache_clack_way; // clack way 481 sc_signal<size_t> r_dcache_clack_set; // clack set 482 482 483 483 // dcache flush handling 484 sc_signal<size_t> r_dcache_flush_count; 484 sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush 485 485 486 486 // ll response handling 487 sc_signal<size_t> r_dcache_ll_rsp_count; 487 sc_signal<size_t> r_dcache_ll_rsp_count; // flit counter used for ll rsp 488 488 489 489 // used by the TLB miss sub-fsm 490 sc_signal<uint32_t> r_dcache_tlb_vaddr; 491 sc_signal<bool> r_dcache_tlb_ins; 492 sc_signal<paddr_t> r_dcache_tlb_paddr; 493 sc_signal<uint32_t> r_dcache_tlb_pte_flags; 494 sc_signal<uint32_t> r_dcache_tlb_pte_ppn; 495 sc_signal<size_t> r_dcache_tlb_cache_way; 496 sc_signal<size_t> r_dcache_tlb_cache_set; 497 sc_signal<size_t> r_dcache_tlb_cache_word; 498 sc_signal<size_t> r_dcache_tlb_way; 499 sc_signal<size_t> r_dcache_tlb_set; 490 sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss 491 sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true) 492 sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte 493 sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2 494 sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2 495 sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache 496 sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache 497 sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache 498 sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb 499 sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb 500 500 501 501 // ITLB and DTLB invalidation 502 sc_signal<paddr_t> r_dcache_tlb_inval_line; 502 sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index 503 503 sc_signal<size_t> r_dcache_tlb_inval_set; // tlb set counter 504 504 … … 508 508 509 509 // Filp-Flop in DCACHE FSM for saving the cleanup victim request 510 sc_signal<bool> r_dcache_cleanup_victim_req; 510 sc_signal<bool> r_dcache_cleanup_victim_req; 511 511 sc_signal<bool> r_dcache_cleanup_victim_line_ncc; 512 512 sc_signal<bool> r_dcache_cleanup_victim_updt_data; … … 551 551 /////////////////////////////////// 552 552 sc_signal<int> r_vci_cmd_fsm; 553 sc_signal<size_t> r_vci_cmd_min; 554 sc_signal<size_t> r_vci_cmd_max; 555 sc_signal<size_t> r_vci_cmd_cpt; 556 sc_signal<bool> r_vci_cmd_imiss_prio; 553 sc_signal<size_t> r_vci_cmd_min; // used for write bursts 554 sc_signal<size_t> r_vci_cmd_max; // used for write bursts 555 sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts 556 sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss 557 557 558 558 /////////////////////////////////// … … 563 563 sc_signal<bool> r_vci_rsp_ins_error; 564 564 sc_signal<bool> r_vci_rsp_data_error; 565 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; 566 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; 565 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM 566 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM 567 567 568 568 … … 595 595 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set 596 596 sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; // cc_receive update table index 597 sc_signal<paddr_t> r_cc_receive_icache_nline; 597 sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address 598 598 599 599 // communication between CC_RECEIVE FSM and DCACHE FSM … … 603 603 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set 604 604 sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index 605 sc_signal<paddr_t> r_cc_receive_dcache_nline; 605 sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address 606 606 sc_signal<bool> r_cc_receive_dcache_inval_is_config; // inval from memcache is config 607 607 … … 611 611 sc_signal<bool> r_dspin_clack_req; 612 612 sc_signal<uint64_t> r_dspin_clack_flit; 613 613 614 614 ////////////////////////////////////////////////////////////////// 615 615 // processor, write buffer, caches , TLBs … … 617 617 618 618 iss_t r_iss; 619 MultiWriteBuffer<paddr_t> 620 GenericCache<paddr_t> 621 GenericCache<paddr_t> 622 GenericTlb<paddr_t> 623 GenericTlb<paddr_t> 619 MultiWriteBuffer<paddr_t> r_wbuf; 620 GenericCache<paddr_t> r_icache; 621 GenericCache<paddr_t> r_dcache; 622 GenericTlb<paddr_t> r_itlb; 623 GenericTlb<paddr_t> r_dtlb; 624 624 625 625 ////////////////////////////////////////////////////////////////// … … 648 648 uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE 649 649 650 uint32_t m_cpt_frz_cycles; 651 uint32_t m_cpt_total_cycles; 650 uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen 651 uint32_t m_cpt_total_cycles; // total number of cycles 652 652 653 653 // Cache activity counters … … 764 764 uint32_t m_cpt_fsm_cc_send [64]; 765 765 766 uint32_t m_cpt_stop_simulation; 767 bool m_monitor_ok; // used to debug cache output768 uint32_t m_monitor_base; 769 uint32_t m_monitor_length; 766 uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen 767 bool m_monitor_ok; // used to debug cache output 768 uint32_t m_monitor_base; 769 uint32_t m_monitor_length; 770 770 771 771 protected: … … 807 807 void start_monitor(paddr_t,paddr_t); 808 808 void stop_monitor(); 809 inline void iss_set_debug_mask(uint v) 810 { 811 809 inline void iss_set_debug_mask(uint v) 810 { 811 r_iss.set_debug_mask(v); 812 812 } 813 813
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