- Timestamp:
- Oct 1, 2014, 5:44:55 PM (10 years ago)
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branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r824 r827 35 35 #include <inttypes.h> 36 36 #include <systemc> 37 38 37 #include "caba_base_module.h" 39 38 #include "multi_write_buffer.h" … … 307 306 soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table; 308 307 309 const size_t 310 const size_t 311 const size_t 312 const size_t 313 const size_t 314 const size_t 315 const size_t 316 const size_t 317 const size_t 318 const paddr_t 319 const size_t 320 const size_t 321 const size_t 322 const paddr_t 323 const size_t 324 const size_t 325 const size_t 326 const size_t 327 const uint32_t 328 const size_t 329 uint32_t 330 bool 331 332 uint32_t 333 uint32_t 308 const size_t m_srcid; 309 const size_t m_cc_global_id; 310 const size_t m_nline_width; 311 const size_t m_itlb_ways; 312 const size_t m_itlb_sets; 313 const size_t m_dtlb_ways; 314 const size_t m_dtlb_sets; 315 const size_t m_icache_ways; 316 const size_t m_icache_sets; 317 const paddr_t m_icache_yzmask; 318 const size_t m_icache_words; 319 const size_t m_dcache_ways; 320 const size_t m_dcache_sets; 321 const paddr_t m_dcache_yzmask; 322 const size_t m_dcache_words; 323 const size_t m_x_width; 324 const size_t m_y_width; 325 const size_t m_proc_id; 326 const uint32_t m_max_frozen_cycles; 327 const size_t m_paddr_nbits; 328 uint32_t m_debug_start_cycle; 329 bool m_debug_ok; 330 331 uint32_t m_dcache_paddr_ext_reset; 332 uint32_t m_icache_paddr_ext_reset; 334 333 335 334 //////////////////////////////////////// … … 344 343 // debug variables 345 344 ///////////////////////////////////////////// 346 bool 347 bool 348 bool 345 bool m_debug_previous_i_hit; 346 bool m_debug_previous_d_hit; 347 bool m_debug_activated; 349 348 350 349 /////////////////////////////// 351 350 // Software visible REGISTERS 352 351 /////////////////////////////// 353 sc_signal<uint32_t> r_mmu_ptpr;// page table pointer register354 sc_signal<uint32_t> r_mmu_mode;// mmu mode register355 sc_signal<uint32_t> r_mmu_word_lo;// mmu misc data low356 sc_signal<uint32_t> r_mmu_word_hi;// mmu misc data hight357 sc_signal<uint32_t> r_mmu_ibvar;// mmu bad instruction address358 sc_signal<uint32_t> r_mmu_dbvar;// mmu bad data address359 sc_signal<uint32_t> r_mmu_ietr;// mmu instruction error type360 sc_signal<uint32_t> r_mmu_detr;// mmu data error type361 uint32_t r_mmu_params;// read-only362 uint32_t r_mmu_release;// read_only352 sc_signal<uint32_t> r_mmu_ptpr; // page table pointer register 353 sc_signal<uint32_t> r_mmu_mode; // mmu mode register 354 sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low 355 sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight 356 sc_signal<uint32_t> r_mmu_ibvar; // mmu bad instruction address 357 sc_signal<uint32_t> r_mmu_dbvar; // mmu bad data address 358 sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type 359 sc_signal<uint32_t> r_mmu_detr; // mmu data error type 360 uint32_t r_mmu_params; // read-only 361 uint32_t r_mmu_release; // read_only 363 362 364 363 … … 366 365 // ICACHE FSM REGISTERS 367 366 ////////////////////////////// 368 sc_signal<int> r_icache_fsm;// state register369 sc_signal<int> r_icache_fsm_save;// return state for coherence op370 sc_signal<paddr_t> r_icache_vci_paddr;// physical address371 sc_signal<uint32_t> r_icache_vaddr_save;// virtual address from processor367 sc_signal<int> r_icache_fsm; // state register 368 sc_signal<int> r_icache_fsm_save; // return state for coherence op 369 sc_signal<paddr_t> r_icache_vci_paddr; // physical address 370 sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor 372 371 373 372 // icache miss handling 374 sc_signal<size_t> r_icache_miss_way;// selected way for cache update375 sc_signal<size_t> r_icache_miss_set;// selected set for cache update376 sc_signal<size_t> r_icache_miss_word;// word index ( cache update)377 sc_signal<bool> r_icache_miss_inval;// coherence request matching a miss378 sc_signal<bool> r_icache_miss_clack;// waiting for a cleanup acknowledge373 sc_signal<size_t> r_icache_miss_way; // selected way for cache update 374 sc_signal<size_t> r_icache_miss_set; // selected set for cache update 375 sc_signal<size_t> r_icache_miss_word; // word index ( cache update) 376 sc_signal<bool> r_icache_miss_inval; // coherence request matching a miss 377 sc_signal<bool> r_icache_miss_clack; // waiting for a cleanup acknowledge 379 378 380 379 // coherence request handling 381 sc_signal<size_t> r_icache_cc_way;// selected way for cc update/inval382 sc_signal<size_t> r_icache_cc_set;// selected set for cc update/inval383 sc_signal<size_t> r_icache_cc_word;// word counter for cc update384 sc_signal<bool> r_icache_cc_need_write;// activate the cache for writing380 sc_signal<size_t> r_icache_cc_way; // selected way for cc update/inval 381 sc_signal<size_t> r_icache_cc_set; // selected set for cc update/inval 382 sc_signal<size_t> r_icache_cc_word; // word counter for cc update 383 sc_signal<bool> r_icache_cc_need_write; // activate the cache for writing 385 384 386 385 // coherence clack handling 387 sc_signal<bool> r_icache_clack_req;// clack request388 sc_signal<size_t> r_icache_clack_way;// clack way389 sc_signal<size_t> r_icache_clack_set;// clack set386 sc_signal<bool> r_icache_clack_req; // clack request 387 sc_signal<size_t> r_icache_clack_way; // clack way 388 sc_signal<size_t> r_icache_clack_set; // clack set 390 389 391 390 // icache flush handling 392 sc_signal<size_t> r_icache_flush_count;// slot counter used for cache flush391 sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush 393 392 394 393 // communication between ICACHE FSM and VCI_CMD FSM 395 sc_signal<bool> r_icache_miss_req;// cached read miss396 sc_signal<bool> r_icache_unc_req;// uncached read miss394 sc_signal<bool> r_icache_miss_req; // cached read miss 395 sc_signal<bool> r_icache_unc_req; // uncached read miss 397 396 398 397 // communication between ICACHE FSM and DCACHE FSM 399 sc_signal<bool> r_icache_tlb_miss_req;// (set icache/reset dcache)400 sc_signal<bool> r_icache_tlb_rsp_error;// tlb miss response error398 sc_signal<bool> r_icache_tlb_miss_req; // (set icache/reset dcache) 399 sc_signal<bool> r_icache_tlb_rsp_error; // tlb miss response error 401 400 402 401 // Flip-Flop in ICACHE FSM for saving the cleanup victim request 403 sc_signal<bool> 404 sc_signal<paddr_t> 402 sc_signal<bool> r_icache_cleanup_victim_req; 403 sc_signal<paddr_t> r_icache_cleanup_victim_nline; 405 404 406 405 // communication between ICACHE FSM and CC_SEND FSM 407 sc_signal<bool> r_icache_cc_send_req;// ICACHE cc_send request408 sc_signal<int> r_icache_cc_send_type;// ICACHE cc_send request type409 sc_signal<paddr_t> r_icache_cc_send_nline;// ICACHE cc_send nline410 sc_signal<size_t> r_icache_cc_send_way;// ICACHE cc_send way411 sc_signal<size_t> r_icache_cc_send_updt_tab_idx;// ICACHE cc_send update table index406 sc_signal<bool> r_icache_cc_send_req; // ICACHE cc_send request 407 sc_signal<int> r_icache_cc_send_type; // ICACHE cc_send request type 408 sc_signal<paddr_t> r_icache_cc_send_nline; // ICACHE cc_send nline 409 sc_signal<size_t> r_icache_cc_send_way; // ICACHE cc_send way 410 sc_signal<size_t> r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index 412 411 413 412 // Physical address extension for data access 414 sc_signal<uint32_t> r_icache_paddr_ext;// CP2 register (if vci_address > 32)413 sc_signal<uint32_t> r_icache_paddr_ext; // CP2 register (if vci_address > 32) 415 414 416 415 /////////////////////////////// 417 416 // DCACHE FSM REGISTERS 418 417 /////////////////////////////// 419 sc_signal<int> r_dcache_fsm;// state register420 sc_signal<int> r_dcache_fsm_cc_save;// return state for coherence op421 sc_signal<int> r_dcache_fsm_scan_save;// return state for tlb scan op418 sc_signal<int> r_dcache_fsm; // state register 419 sc_signal<int> r_dcache_fsm_cc_save; // return state for coherence op 420 sc_signal<int> r_dcache_fsm_scan_save; // return state for tlb scan op 422 421 // registers written in P0 stage (used in P1 stage) 423 sc_signal<bool> r_dcache_wbuf_req;// WBUF must be written in P1 stage424 sc_signal<bool> r_dcache_updt_req;// DCACHE must be updated in P1 stage425 sc_signal<uint32_t> r_dcache_save_vaddr;// virtual address (from proc)426 sc_signal<uint32_t> r_dcache_save_wdata;// write data (from proc)427 sc_signal<uint32_t> r_dcache_save_be;// byte enable (from proc)428 sc_signal<paddr_t> r_dcache_save_paddr;// physical address429 sc_signal<size_t> r_dcache_save_cache_way;// selected way (from dcache)430 sc_signal<size_t> r_dcache_save_cache_set;// selected set (from dcache)431 sc_signal<size_t> r_dcache_save_cache_word;// selected word (from dcache)422 sc_signal<bool> r_dcache_wbuf_req; // WBUF must be written in P1 stage 423 sc_signal<bool> r_dcache_updt_req; // DCACHE must be updated in P1 stage 424 sc_signal<uint32_t> r_dcache_save_vaddr; // virtual address (from proc) 425 sc_signal<uint32_t> r_dcache_save_wdata; // write data (from proc) 426 sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) 427 sc_signal<paddr_t> r_dcache_save_paddr; // physical address 428 sc_signal<size_t> r_dcache_save_cache_way; // selected way (from dcache) 429 sc_signal<size_t> r_dcache_save_cache_set; // selected set (from dcache) 430 sc_signal<size_t> r_dcache_save_cache_word; // selected word (from dcache) 432 431 // registers used by the Dirty bit sub-fsm 433 sc_signal<paddr_t> r_dcache_dirty_paddr;// PTE physical address434 sc_signal<size_t> r_dcache_dirty_way;// way to invalidate in dcache435 sc_signal<size_t> r_dcache_dirty_set;// set to invalidate in dcache432 sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address 433 sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache 434 sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache 436 435 437 436 // communication between DCACHE FSM and VCI_CMD FSM 438 sc_signal<paddr_t> r_dcache_vci_paddr;// physical address for VCI command439 sc_signal<uint32_t> r_dcache_vci_wdata;// write unc data for VCI command440 sc_signal<bool> r_dcache_vci_miss_req;// read miss request441 sc_signal<bool> r_dcache_vci_unc_req;// uncacheable request (read/write)442 sc_signal<uint32_t> r_dcache_vci_unc_be;// uncacheable byte enable443 sc_signal<uint32_t> r_dcache_vci_unc_write;// uncacheable data write request444 sc_signal<bool> r_dcache_vci_cas_req;// atomic write request CAS445 sc_signal<uint32_t> r_dcache_vci_cas_old;// previous data value for a CAS446 sc_signal<uint32_t> r_dcache_vci_cas_new;// new data value for a CAS447 sc_signal<bool> r_dcache_vci_ll_req;// atomic read request LL448 sc_signal<bool> r_dcache_vci_sc_req;// atomic write request SC449 sc_signal<uint32_t> r_dcache_vci_sc_data;// SC data (command)437 sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command 438 sc_signal<uint32_t> r_dcache_vci_wdata; // write unc data for VCI command 439 sc_signal<bool> r_dcache_vci_miss_req; // read miss request 440 sc_signal<bool> r_dcache_vci_unc_req; // uncacheable request (read/write) 441 sc_signal<uint32_t> r_dcache_vci_unc_be; // uncacheable byte enable 442 sc_signal<uint32_t> r_dcache_vci_unc_write; // uncacheable data write request 443 sc_signal<bool> r_dcache_vci_cas_req; // atomic write request CAS 444 sc_signal<uint32_t> r_dcache_vci_cas_old; // previous data value for a CAS 445 sc_signal<uint32_t> r_dcache_vci_cas_new; // new data value for a CAS 446 sc_signal<bool> r_dcache_vci_ll_req; // atomic read request LL 447 sc_signal<bool> r_dcache_vci_sc_req; // atomic write request SC 448 sc_signal<uint32_t> r_dcache_vci_sc_data; // SC data (command) 450 449 451 450 //RWT: local cas 452 sc_signal<bool> 453 sc_signal<size_t> 454 sc_signal<size_t> 455 sc_signal<size_t> 451 sc_signal<bool> r_cas_islocal; 452 sc_signal<size_t> r_cas_local_way; 453 sc_signal<size_t> r_cas_local_set; 454 sc_signal<size_t> r_cas_local_word; 456 455 457 456 // register used for XTN inval 458 sc_signal<size_t> r_dcache_xtn_way;// selected way (from dcache)459 sc_signal<size_t> r_dcache_xtn_set;// selected set (from dcache)457 sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) 458 sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) 460 459 461 460 // handling dcache miss 462 sc_signal<int> r_dcache_miss_type;// depending on the requester463 sc_signal<size_t> r_dcache_miss_word;// word index for cache update464 sc_signal<size_t> r_dcache_miss_way;// selected way for cache update465 sc_signal<size_t> r_dcache_miss_set;// selected set for cache update466 sc_signal<bool> r_dcache_miss_inval;// coherence request matching a miss467 sc_signal<bool> r_dcache_miss_clack;// waiting for a cleanup acknowledge461 sc_signal<int> r_dcache_miss_type; // depending on the requester 462 sc_signal<size_t> r_dcache_miss_word; // word index for cache update 463 sc_signal<size_t> r_dcache_miss_way; // selected way for cache update 464 sc_signal<size_t> r_dcache_miss_set; // selected set for cache update 465 sc_signal<bool> r_dcache_miss_inval; // coherence request matching a miss 466 sc_signal<bool> r_dcache_miss_clack; // waiting for a cleanup acknowledge 468 467 469 468 // handling coherence requests 470 sc_signal<size_t> r_dcache_cc_way;// selected way for cc update/inval471 sc_signal<size_t> r_dcache_cc_set;// selected set for cc update/inval472 sc_signal<int> r_dcache_cc_state;// state of selected cache slot473 sc_signal<size_t> r_dcache_cc_word;// word counter for cc update474 sc_signal<bool> r_dcache_cc_need_write;// activate the cache for writing475 sc_signal<paddr_t> r_dcache_cc_inval_addr;// address for a cleanup transaction476 sc_signal<uint32_t> 469 sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval 470 sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval 471 sc_signal<int> r_dcache_cc_state; // state of selected cache slot 472 sc_signal<size_t> r_dcache_cc_word; // word counter for cc update 473 sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing 474 sc_signal<paddr_t> r_dcache_cc_inval_addr; // address for a cleanup transaction 475 sc_signal<uint32_t> r_dcache_cc_inval_data_cpt; 477 476 478 477 // coherence clack handling 479 sc_signal<bool> r_dcache_clack_req;// clack request480 sc_signal<size_t> r_dcache_clack_way;// clack way481 sc_signal<size_t> r_dcache_clack_set;// clack set478 sc_signal<bool> r_dcache_clack_req; // clack request 479 sc_signal<size_t> r_dcache_clack_way; // clack way 480 sc_signal<size_t> r_dcache_clack_set; // clack set 482 481 483 482 // dcache flush handling 484 sc_signal<size_t> r_dcache_flush_count;// slot counter used for cache flush483 sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush 485 484 486 485 // ll response handling 487 sc_signal<size_t> r_dcache_ll_rsp_count;// flit counter used for ll rsp486 sc_signal<size_t> r_dcache_ll_rsp_count; // flit counter used for ll rsp 488 487 489 488 // used by the TLB miss sub-fsm 490 sc_signal<uint32_t> r_dcache_tlb_vaddr;// virtual address for a tlb miss491 sc_signal<bool> r_dcache_tlb_ins;// target tlb (itlb if true)492 sc_signal<paddr_t> r_dcache_tlb_paddr;// physical address of pte493 sc_signal<uint32_t> r_dcache_tlb_pte_flags;// pte1 or first word of pte2494 sc_signal<uint32_t> r_dcache_tlb_pte_ppn;// second word of pte2495 sc_signal<size_t> r_dcache_tlb_cache_way;// selected way in dcache496 sc_signal<size_t> r_dcache_tlb_cache_set;// selected set in dcache497 sc_signal<size_t> r_dcache_tlb_cache_word;// selected word in dcache498 sc_signal<size_t> r_dcache_tlb_way;// selected way in tlb499 sc_signal<size_t> r_dcache_tlb_set;// selected set in tlb489 sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss 490 sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true) 491 sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte 492 sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2 493 sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2 494 sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache 495 sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache 496 sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache 497 sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb 498 sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb 500 499 501 500 // ITLB and DTLB invalidation 502 sc_signal<paddr_t> r_dcache_tlb_inval_line;// line index503 sc_signal<size_t> r_dcache_tlb_inval_set;// tlb set counter501 sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index 502 sc_signal<size_t> r_dcache_tlb_inval_set; // tlb set counter 504 503 505 504 // communication between DCACHE FSM and ICACHE FSM 506 sc_signal<bool> r_dcache_xtn_req;// xtn request (caused by processor)507 sc_signal<int> r_dcache_xtn_opcode;// xtn request type505 sc_signal<bool> r_dcache_xtn_req; // xtn request (caused by processor) 506 sc_signal<int> r_dcache_xtn_opcode; // xtn request type 508 507 509 508 // Filp-Flop in DCACHE FSM for saving the cleanup victim request 510 sc_signal<bool> 511 sc_signal<bool> 512 sc_signal<bool> 513 sc_signal<paddr_t> 509 sc_signal<bool> r_dcache_cleanup_victim_req; 510 sc_signal<bool> r_dcache_cleanup_victim_line_ncc; 511 sc_signal<bool> r_dcache_cleanup_victim_updt_data; 512 sc_signal<paddr_t> r_dcache_cleanup_victim_nline; 514 513 515 514 // communication between DCACHE FSM and CC_SEND FSM 516 sc_signal<bool> r_dcache_cc_send_req;// DCACHE cc_send request517 sc_signal<int> r_dcache_cc_send_type;// DCACHE cc_send request type518 sc_signal<paddr_t> r_dcache_cc_send_nline;// DCACHE cc_send nline519 sc_signal<size_t> r_dcache_cc_send_way;// DCACHE cc_send way520 sc_signal<size_t> r_dcache_cc_send_updt_tab_idx;// DCACHE cc_send update table index515 sc_signal<bool> r_dcache_cc_send_req; // DCACHE cc_send request 516 sc_signal<int> r_dcache_cc_send_type; // DCACHE cc_send request type 517 sc_signal<paddr_t> r_dcache_cc_send_nline; // DCACHE cc_send nline 518 sc_signal<size_t> r_dcache_cc_send_way; // DCACHE cc_send way 519 sc_signal<size_t> r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index 521 520 522 521 // special registers for RWT 523 sc_signal<bool> r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt) 524 sc_signal<bool> r_dcache_cc_cleanup_line_ncc; // Register for cleanup with data (wb updt) 525 sc_signal<bool> r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode 526 sc_signal<bool> r_dcache_line_no_coherence; // Register for line current in no coherence mode 527 sc_signal<bool> r_dcache_dirty_save; 528 sc_signal<uint32_t> r_cc_send_cpt_word; 529 sc_signal<uint32_t> r_dcache_miss_data_cpt; 530 sc_signal<paddr_t> r_dcache_miss_data_addr; 531 sc_signal<uint32_t> r_dcache_xtn_flush_data_cpt; 532 sc_signal<paddr_t> r_dcache_xtn_flush_addr_data; 533 sc_signal<int> r_dcache_xtn_state; 534 sc_signal<paddr_t> r_dcache_xtn_data_addr; 535 sc_signal<uint32_t> r_dcache_xtn_data_cpt; 536 sc_signal<bool> r_dcache_read_state; 522 sc_signal<bool> r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt) 523 sc_signal<bool> r_dcache_cc_cleanup_line_ncc; // Register for cleanup with data (wb updt) 524 sc_signal<bool> r_dcache_dirty_save; 525 sc_signal<uint32_t> r_cc_send_cpt_word; 526 sc_signal<uint32_t> r_dcache_miss_data_cpt; 527 sc_signal<paddr_t> r_dcache_miss_data_addr; 528 sc_signal<uint32_t> r_dcache_xtn_flush_data_cpt; 529 sc_signal<paddr_t> r_dcache_xtn_flush_addr_data; 530 sc_signal<int> r_dcache_xtn_state; 531 sc_signal<paddr_t> r_dcache_xtn_data_addr; 532 sc_signal<uint32_t> r_dcache_xtn_data_cpt; 533 sc_signal<bool> r_dcache_read_state; 537 534 538 535 // dcache directory extension 539 int 536 int *r_dcache_content_state; // content state of one cache line 540 537 // Stats 541 int 542 bool 538 int *r_dcache_dirty_word; // use for compute number of words dirty per cleanup_data 539 bool *r_dcache_zombi_ncc; // use for compute number of blocked write on ncc zombi line 543 540 ////////////////////////////////////////////////////////////////////////////////////// 544 541 545 542 /////////////////////////////////// 546 543 // Physical address extension for data access 547 sc_signal<uint32_t> r_dcache_paddr_ext;// CP2 register (if vci_address > 32)544 sc_signal<uint32_t> r_dcache_paddr_ext; // CP2 register (if vci_address > 32) 548 545 549 546 /////////////////////////////////// 550 547 // VCI_CMD FSM REGISTERS 551 548 /////////////////////////////////// 552 sc_signal<int> 553 sc_signal<size_t> r_vci_cmd_min;// used for write bursts554 sc_signal<size_t> r_vci_cmd_max;// used for write bursts555 sc_signal<size_t> r_vci_cmd_cpt;// used for write bursts556 sc_signal<bool> r_vci_cmd_imiss_prio;// round-robin between imiss & dmiss549 sc_signal<int> r_vci_cmd_fsm; 550 sc_signal<size_t> r_vci_cmd_min; // used for write bursts 551 sc_signal<size_t> r_vci_cmd_max; // used for write bursts 552 sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts 553 sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss 557 554 558 555 /////////////////////////////////// 559 556 // VCI_RSP FSM REGISTERS 560 557 /////////////////////////////////// 561 sc_signal<int> 562 sc_signal<size_t> 563 sc_signal<bool> 564 sc_signal<bool> 565 GenericFifo<uint32_t> r_vci_rsp_fifo_icache;// response FIFO to ICACHE FSM566 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache;// response FIFO to DCACHE FSM558 sc_signal<int> r_vci_rsp_fsm; 559 sc_signal<size_t> r_vci_rsp_cpt; 560 sc_signal<bool> r_vci_rsp_ins_error; 561 sc_signal<bool> r_vci_rsp_data_error; 562 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM 563 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM 567 564 568 565 569 566 //RWT 570 GenericFifo<bool> 571 GenericFifo<uint32_t> 567 GenericFifo<bool> r_vci_rsp_fifo_rpktid; 568 GenericFifo<uint32_t> r_cc_send_data_fifo; 572 569 573 570 /////////////////////////////////// 574 571 // CC_SEND FSM REGISTER 575 572 /////////////////////////////////// 576 sc_signal<int> r_cc_send_fsm;// state register577 sc_signal<bool> r_cc_send_last_client;// 0 dcache / 1 icache573 sc_signal<int> r_cc_send_fsm; // state register 574 sc_signal<bool> r_cc_send_last_client; // 0 dcache / 1 icache 578 575 579 576 /////////////////////////////////// 580 577 // CC_RECEIVE FSM REGISTER 581 578 /////////////////////////////////// 582 sc_signal<int> r_cc_receive_fsm;// state register583 sc_signal<bool> r_cc_receive_data_ins;// request to : 0 dcache / 1 icache579 sc_signal<int> r_cc_receive_fsm; // state register 580 sc_signal<bool> r_cc_receive_data_ins; // request to : 0 dcache / 1 icache 584 581 585 582 // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM 586 sc_signal<size_t> r_cc_receive_word_idx;// word index587 GenericFifo<uint32_t> 588 GenericFifo<uint32_t> 589 GenericFifo<bool> 583 sc_signal<size_t> r_cc_receive_word_idx; // word index 584 GenericFifo<uint32_t> r_cc_receive_updt_fifo_be; 585 GenericFifo<uint32_t> r_cc_receive_updt_fifo_data; 586 GenericFifo<bool> r_cc_receive_updt_fifo_eop; 590 587 591 588 // communication between CC_RECEIVE FSM and ICACHE FSM 592 sc_signal<bool> r_cc_receive_icache_req;// cc_receive to icache request593 sc_signal<int> r_cc_receive_icache_type;// cc_receive type of request594 sc_signal<size_t> r_cc_receive_icache_way;// cc_receive to icache way595 sc_signal<size_t> r_cc_receive_icache_set;// cc_receive to icache set596 sc_signal<size_t> r_cc_receive_icache_updt_tab_idx;// cc_receive update table index597 sc_signal<paddr_t> r_cc_receive_icache_nline;// cache line physical address589 sc_signal<bool> r_cc_receive_icache_req; // cc_receive to icache request 590 sc_signal<int> r_cc_receive_icache_type; // cc_receive type of request 591 sc_signal<size_t> r_cc_receive_icache_way; // cc_receive to icache way 592 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set 593 sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; // cc_receive update table index 594 sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address 598 595 599 596 // communication between CC_RECEIVE FSM and DCACHE FSM 600 sc_signal<bool> r_cc_receive_dcache_req;// cc_receive to dcache request601 sc_signal<int> r_cc_receive_dcache_type;// cc_receive type of request602 sc_signal<size_t> r_cc_receive_dcache_way;// cc_receive to dcache way603 sc_signal<size_t> r_cc_receive_dcache_set;// cc_receive to dcache set604 sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx;// cc_receive update table index605 sc_signal<paddr_t> r_cc_receive_dcache_nline;// cache line physical address606 sc_signal<bool> r_cc_receive_dcache_inval_is_config;// inval from memcache is config597 sc_signal<bool> r_cc_receive_dcache_req; // cc_receive to dcache request 598 sc_signal<int> r_cc_receive_dcache_type; // cc_receive type of request 599 sc_signal<size_t> r_cc_receive_dcache_way; // cc_receive to dcache way 600 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set 601 sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index 602 sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address 603 sc_signal<bool> r_cc_receive_dcache_inval_is_config; // inval from memcache is config 607 604 608 605 /////////////////////////////////// 609 606 // DSPIN CLACK INTERFACE REGISTER 610 607 /////////////////////////////////// 611 sc_signal<bool> 612 sc_signal<uint64_t> 608 sc_signal<bool> r_dspin_clack_req; 609 sc_signal<uint64_t> r_dspin_clack_flit; 613 610 614 611 ////////////////////////////////////////////////////////////////// … … 616 613 ////////////////////////////////////////////////////////////////// 617 614 618 iss_t 619 MultiWriteBuffer<paddr_t> 620 GenericCache<paddr_t> 621 GenericCache<paddr_t> 622 GenericTlb<paddr_t> 623 GenericTlb<paddr_t> 615 iss_t r_iss; 616 MultiWriteBuffer<paddr_t> r_wbuf; 617 GenericCache<paddr_t> r_icache; 618 GenericCache<paddr_t> r_dcache; 619 GenericTlb<paddr_t> r_itlb; 620 GenericTlb<paddr_t> r_dtlb; 624 621 625 622 ////////////////////////////////////////////////////////////////// … … 627 624 ////////////////////////////////////////////////////////////////// 628 625 629 sc_signal<paddr_t> r_dcache_llsc_paddr; 630 sc_signal<uint32_t> r_dcache_llsc_key; 631 sc_signal<uint32_t> r_dcache_llsc_count; 632 sc_signal<bool> r_dcache_llsc_valid; 633 634 635 sc_signal<bool> r_cache_frozen; 626 sc_signal<paddr_t> r_dcache_llsc_paddr; 627 sc_signal<uint32_t> r_dcache_llsc_key; 628 sc_signal<uint32_t> r_dcache_llsc_count; 629 sc_signal<bool> r_dcache_llsc_valid; 636 630 637 631 //////////////////////////////// 638 632 // Activity counters 639 633 //////////////////////////////// 640 uint32_t m_cpt_dcache_data_read; 641 uint32_t m_cpt_dcache_data_write; 642 uint32_t m_cpt_dcache_dir_read; 643 uint32_t m_cpt_dcache_dir_write; 644 645 uint32_t m_cpt_icache_data_read; 646 uint32_t m_cpt_icache_data_write; 647 uint32_t m_cpt_icache_dir_read; 648 uint32_t m_cpt_icache_dir_write; 649 650 uint32_t m_cpt_frz_cycles; 651 uint32_t m_cpt_total_cycles; 634 uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ 635 uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE 636 uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ 637 uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE 638 639 uint32_t m_cpt_icache_data_read; // ICACHE DATA READ 640 uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE 641 uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ 642 uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE 643 644 uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen 645 uint32_t m_cpt_total_cycles; // total number of cycles 652 646 653 647 // Cache activity counters 654 uint32_t m_cpt_data_read; 655 uint32_t m_cpt_data_write; 648 uint32_t m_cpt_data_read; // total number of read data 649 uint32_t m_cpt_data_write; // total number of write data 656 650 uint32_t m_cpt_data_write_back; 651 uint32_t m_cpt_data_write_miss; // number of total write miss 652 uint32_t m_cpt_data_write_on_zombi; // number of frozen cycles related to blocked write on ZOMBI line 653 uint32_t m_cpt_data_write_on_zombi_ncc; // number of frozen cycles related to blocked write on NCC ZOMBI line 657 654 uint32_t m_cpt_data_cleanup; 658 655 uint32_t m_cpt_data_sc; 659 uint32_t m_cpt_data_miss; // number of read miss 660 uint32_t m_cpt_ins_miss; // number of instruction miss 661 uint32_t m_cpt_unc_read; // number of read uncached 662 uint32_t m_cpt_write_cached; // number of cached write 663 uint32_t m_cpt_ins_read; // number of instruction read 664 uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss 665 666 uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer 667 uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss 668 uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read 669 uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss 670 671 uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions 672 uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions 673 uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions 674 uint32_t m_cpt_dunc_transaction; // number of VCI uncached read transactions 675 uint32_t m_cpt_ll_transaction; // number of VCI uncached read transactions 676 uint32_t m_cpt_write_transaction; // number of VCI write transactions 677 uint32_t m_cpt_icache_unc_transaction; 678 679 uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions 680 uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions 681 uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions 682 uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions 683 uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions 684 uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions 656 uint32_t m_cpt_dcache_miss; // number of read miss 657 uint32_t m_cpt_icache_miss; // number of instruction miss 658 uint32_t m_cpt_ins_read; // number of instruction read 659 660 uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss 661 uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss 662 663 uint32_t m_cpt_write_transaction; // number of VCI write transactions 664 uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions 685 665 686 666 // TLB activity counters 687 uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read 688 uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss 689 uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update 690 uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line 691 uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache 692 693 uint32_t m_cpt_data_tlb_read; // number of data tlb read 694 uint32_t m_cpt_data_tlb_miss; // number of data tlb miss 695 uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update 696 uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty 697 uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache 698 uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line 667 uint32_t m_cpt_itlb_read; // number of instruction tlb read 668 uint32_t m_cpt_itlb_miss; // number of instruction tlb miss 669 uint32_t m_cpt_itlb_write; // number of instruction tlb update 670 671 uint32_t m_cpt_dtlb_read; // number of data tlb read 672 uint32_t m_cpt_dtlb_miss; // number of data tlb miss 673 uint32_t m_cpt_dtlb_write; // number of data tlb update 674 675 uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss 676 677 // coherence activity counters 678 uint32_t m_cpt_cleanup_data_not_dirty; // number of total cleanup data without extra data flits 679 uint32_t m_cpt_cleanup_data_dirty_word; // number of total words dirty in cleanup data 680 681 682 683 // counters NOT implemented 684 uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer 685 uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read 686 uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions 687 uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions 688 uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions 689 uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions 690 uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions 691 uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions 692 uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions 693 uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty 694 uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache 695 uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache 696 uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss 697 uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc 698 uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc 699 uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty 700 uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions 701 uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions 702 uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions 703 uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions 704 uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands 705 uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets 706 uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets 707 uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets 708 uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets 709 uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets 710 uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets 711 uint32_t m_cpt_dunc_transaction; // number of VCI uncached read transactions 712 uint32_t m_cpt_ll_transaction; // number of VCI uncached read transactions 713 uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands 714 uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands 715 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands 716 uint32_t m_cpt_unc_read; // number of read uncached 717 uint32_t m_cpt_write_cached; // number of cached write 699 718 uint32_t m_cpt_tlb_occup_dcache; 700 719 701 uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss702 uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss703 uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc704 uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc705 uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty706 uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache707 uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache708 709 uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions710 uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions711 uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions712 uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions713 uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions714 uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions715 uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions716 uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions717 718 uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions719 uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions720 uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions721 uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions722 uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions723 uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions724 uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions725 uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions726 727 // coherence activity counters728 uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands729 uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands730 uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands731 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands732 uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands733 734 uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets735 uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets736 uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets737 uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets738 739 uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets740 uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets741 uint32_t m_cpt_cleanup_data_not_dirty; // number of total cleanup data without extra data flits742 uint32_t m_cpt_cleanup_data_dirty_word; // number of total words dirty in cleanup data743 uint32_t m_cpt_data_write_miss; // number of total write miss744 uint32_t m_cpt_data_write_on_zombi; // number of frozen cycles related to blocked write on line NCC/CC ZOMBI745 uint32_t m_cpt_data_write_on_zombi_ncc; // number of frozen cycles related to blocked write on line NCC ZOMBI746 747 uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions748 uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions749 uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions750 uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions751 752 uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate753 uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate754 755 uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate756 uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate757 720 758 721 // FSM activity counters … … 764 727 uint32_t m_cpt_fsm_cc_send [64]; 765 728 766 uint32_t m_cpt_stop_simulation; 767 bool m_monitor_ok; 729 uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen 730 bool m_monitor_ok; // used to debug cache output 768 731 uint32_t m_monitor_base; 769 732 uint32_t m_monitor_length; … … 774 737 public: 775 738 VciCcVCacheWrapper( 776 sc_module_name 777 const int 778 const soclib::common::MappingTable 779 const soclib::common::IntTab 780 const size_t 781 const size_t 782 const size_t 783 const size_t 784 const size_t 785 const size_t 786 const size_t 787 const size_t 788 const size_t 789 const size_t 790 const size_t 791 const size_t 792 const size_t 793 const size_t 794 const size_t 795 const uint32_t 796 const uint32_t 797 const bool 739 sc_module_name name, 740 const int proc_id, 741 const soclib::common::MappingTable &mtd, 742 const soclib::common::IntTab &srcid, 743 const size_t cc_global_id, 744 const size_t itlb_ways, 745 const size_t itlb_sets, 746 const size_t dtlb_ways, 747 const size_t dtlb_sets, 748 const size_t icache_ways, 749 const size_t icache_sets, 750 const size_t icache_words, 751 const size_t dcache_ways, 752 const size_t dcache_sets, 753 const size_t dcache_words, 754 const size_t wbuf_nlines, 755 const size_t wbuf_nwords, 756 const size_t x_width, 757 const size_t y_width, 758 const uint32_t max_frozen_cycles, 759 const uint32_t debug_start_cycle, 760 const bool debug_ok ); 798 761 799 762 ~VciCcVCacheWrapper();
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