Changeset 853 for branches/reconfiguration/modules/vci_cc_vcache_wrapper
- Timestamp:
- Oct 21, 2014, 5:16:36 PM (10 years ago)
- Location:
- branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r846 r853 65 65 66 66 typedef typename vci_param::fast_addr_t paddr_t; 67 typedef typename vci_param::fast_trdid_t trdid_t; 67 68 68 69 enum icache_fsm_state_e … … 441 442 sc_signal<bool> r_dcache_vci_sc_req; // atomic write request SC 442 443 sc_signal<uint32_t> r_dcache_vci_sc_data; // SC data (command) 444 sc_signal<trdid_t> r_dcache_vci_miss_trdid; // miss dcache trdid (for debug) 443 445 444 446 // register used for XTN inval … … 457 459 sc_signal<uint32_t> r_dcache_miss_wdt_max; // wdt triggering value 458 460 sc_signal<uint32_t> r_dcache_miss_wdt; // wdt counter 461 sc_signal<trdid_t> r_dcache_wdt_timeout; // timeout counter (for debug) 459 462 460 463 // handling coherence requests -
branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r846 r853 322 322 r_dcache_vci_sc_req("r_dcache_vci_sc_req"), 323 323 r_dcache_vci_sc_data("r_dcache_vci_sc_data"), 324 r_dcache_vci_miss_trdid("r_dcache_vci_miss_trdid"), 324 325 325 326 r_dcache_xtn_way("r_dcache_xtn_way"), … … 333 334 r_dcache_miss_wdt_max("r_dcache_miss_wdt_max"), 334 335 r_dcache_miss_wdt("r_dcache_miss_wdt"), 336 r_dcache_wdt_timeout("r_dcache_wdt_timeout"), 335 337 336 338 r_dcache_cc_way("r_dcache_cc_way"), … … 816 818 // Reset watchdog timer threshold to max value 817 819 r_dcache_miss_wdt_max = UINT32_MAX; 820 r_dcache_wdt_timeout = 0; 818 821 819 822 // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs … … 2799 2802 #endif 2800 2803 // request a VCI DMISS transaction 2804 r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read(); 2805 2801 2806 r_dcache_vci_paddr = paddr; 2802 2807 r_dcache_vci_miss_req = true; … … 3194 3199 else // we must load the missing cache line in dcache 3195 3200 { 3201 r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read(); 3202 3196 3203 r_dcache_vci_miss_req = true; 3197 3204 r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); … … 3469 3476 else // we must load the missing cache line in dcache 3470 3477 { 3478 r_dcache_vci_miss_trdid = r_dcache_wdt_timeout.read(); 3479 3471 3480 r_dcache_fsm = DCACHE_MISS_SELECT; 3472 3481 r_dcache_vci_miss_req = true; … … 4296 4305 m_drsp.error = true; 4297 4306 r_dcache_fsm = DCACHE_IDLE; 4307 4308 // debug: this counter is used to detect an early WDT timeout. 4309 // It is sent as the data miss transactions TRDID. When a data miss 4310 // response is treated by the RSP FSM, the RTRDID is compared to 4311 // this counter to determine if a timeout was triggered during the 4312 // transaction. 4313 r_dcache_wdt_timeout = r_dcache_wdt_timeout.read() + 1; 4314 4315 #if DEBUG_DCACHE 4316 if (m_debug_dcache_fsm) 4317 { 4318 std::cout << " <PROC " << name() << " DCACHE_MISS_WAIT>" 4319 " watchdog timer exception" << std::endl; 4320 } 4321 #endif 4298 4322 break; 4299 4323 } … … 5371 5395 r_vci_rsp_cpt = 0; 5372 5396 5373 if ((p_vci.rpktid.read() & 0x7) == 5397 if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC) 5374 5398 { 5375 5399 r_vci_rsp_fsm = RSP_DATA_UNC; 5376 5400 } 5377 else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS) 5378 { 5401 else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS) 5402 { 5403 // debug: verify that the available response concerns the current transaction. 5404 assert(r_dcache_wdt_timeout.read() == p_vci.rtrdid.read()); 5405 5379 5406 r_vci_rsp_fsm = RSP_DATA_MISS; 5380 5407 } 5381 else if ((p_vci.rpktid.read() & 0x7) == 5408 else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC) 5382 5409 { 5383 5410 r_vci_rsp_fsm = RSP_INS_UNC; 5384 5411 } 5385 else if ((p_vci.rpktid.read() & 0x7) == 5412 else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS) 5386 5413 { 5387 5414 r_vci_rsp_fsm = RSP_INS_MISS; 5388 5415 } 5389 else if ((p_vci.rpktid.read() & 0x7) == 5416 else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE) 5390 5417 { 5391 5418 r_vci_rsp_fsm = RSP_DATA_WRITE; 5392 5419 } 5393 else if ((p_vci.rpktid.read() & 0x7) == 5420 else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS) 5394 5421 { 5395 5422 r_vci_rsp_fsm = RSP_DATA_UNC; 5396 5423 } 5397 else if ((p_vci.rpktid.read() & 0x7) == 5424 else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL) 5398 5425 { 5399 5426 r_vci_rsp_fsm = RSP_DATA_LL; … … 6074 6101 p_vci.wdata = 0; 6075 6102 p_vci.be = 0xF; 6076 p_vci.trdid = 0;6103 p_vci.trdid = r_dcache_vci_miss_trdid.read(); 6077 6104 p_vci.pktid = TYPE_READ_DATA_MISS; 6078 6105 p_vci.plen = m_dcache_words << 2;
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