Changeset 912 for trunk/modules/vci_mem_cache/caba/source/src
- Timestamp:
- Jan 2, 2015, 1:18:51 PM (10 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r908 r912 469 469 r_alloc_heap_fsm("r_alloc_heap_fsm"), 470 470 r_alloc_heap_reset_cpt("r_alloc_heap_reset_cpt") 471 471 472 #if MONITOR_MEMCACHE_FSM == 1 472 473 , … … 879 880 } 880 881 881 ///////////////////////////////////////// 882 ////////////////////////////////////////////////////////////// 882 883 tmpl(void)::print_stats(bool activity_counters, bool stats) 883 ///////////////////////////////////////// 884 ///////////////////////////////////////////////////////////// 884 885 { 885 886 std::cout << "**********************************" << std::dec << std::endl; … … 1058 1059 1059 1060 r_config_cmd = MEMC_CMD_NOP; 1060 r_config_lock = false;1061 1061 1062 1062 m_config_to_cc_send_inst_fifo.init(); … … 1448 1448 case MEMC_CONFIG: 1449 1449 { 1450 if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock 1451 and (regr == MEMC_LOCK)) 1452 { 1453 rdata = (uint32_t) r_config_lock.read(); 1454 need_rsp = true; 1455 error = 0; 1456 r_config_lock = true; 1457 } 1458 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock 1459 and (regr == MEMC_LOCK)) 1460 { 1461 need_rsp = true; 1462 error = 0; 1463 r_config_lock = false; 1464 } 1465 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo 1450 if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo 1466 1451 and (regr == MEMC_ADDR_LO)) 1467 1452 { … … 1992 1977 // CONFIG FSM 1993 1978 //////////////////////////////////////////////////////////////////////////////////// 1994 // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC).1979 // The CONFIG FSM handles the L2/L3 coherence requests: 1995 1980 // The target buffer can have any size, and there is one single command for 1996 1981 // all cache lines covered by the target buffer. 1997 // 1998 // An INVAL or SYNC configuration operation is defined by the following registers: 1982 // An INVAL or SYNC operation is defined by the following registers: 1999 1983 // - bool r_config_cmd : INVAL / SYNC / NOP 2000 1984 // - uint64_t r_config_address : buffer base address … … 2036 2020 // The CONFIG SYNC response is sent only when the last PUT response is received. 2037 2021 // 2038 // From the software point of view, a configuration request is a sequence 2039 // of 6 atomic accesses in an uncached segment. A dedicated lock is used 2040 // to handle only one configuration command at a given time: 2041 // - Read MEMC_LOCK : Get the lock 2022 // From the software point of view, a L2/L3 coherence request is a sequence 2023 // of 4 atomic accesses in an uncached segment: 2042 2024 // - Write MEMC_ADDR_LO : Set the buffer address LSB 2043 2025 // - Write MEMC_ADDR_HI : Set the buffer address MSB 2044 2026 // - Write MEMC_BUF_LENGTH : set buffer length (bytes) 2045 2027 // - Write MEMC_CMD_TYPE : launch the actual operation 2046 // - WRITE MEMC_LOCK : release the lock2047 2028 //////////////////////////////////////////////////////////////////////////////////// 2048 2029
Note: See TracChangeset
for help on using the changeset viewer.