Changeset 937
- Timestamp:
- Feb 1, 2015, 5:06:41 PM (10 years ago)
- Location:
- trunk/platforms/tsar_generic_leti
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_leti/arch.py
r870 r937 11 11 # This file contains a mapping generator for the "tsar_generic_leti" platform. 12 12 # This includes both the hardware architecture (clusters, processors, 13 # peripherals, physical space segmentation) and the mapping of all kernel 14 # objects (global vsegs). 15 # 16 # The "constructor" parameters are: 17 # - x_size : number of clusters in a row 18 # - y_size : number of clusters in a column 19 # - nb_procs : number of processors per cluster 13 # peripherals, physical space segmentation) and the mapping of all boot 14 # and kernel objects (global vsegs). 15 # 16 # The x_size & y_size parameters define the total number of clusters. 17 # The upper row (y = y_size-1) does not contain processors or memory. 18 # 19 # It does not use the IOB component: 20 # The external peripherals are located in cluster[x_size-1][y_size-1]. 21 # 22 # It does not use an external ROM, as the preloader code is (pre)loaded 23 # at address 0x0, in the physical memory of cluster[0][0]. 24 # 25 # It can use an - optional - RAMDISK located in cluster[0][0]. 26 # 27 # The others hardware parameters are: 20 28 # - fbf_width : frame_buffer width = frame_buffer heigth 21 #22 # The "hidden" parameters (defined below) are:23 29 # - nb_ttys : number of TTY channels 24 30 # - nb_nics : number of NIC channels 25 # - x_io : cluster_io x coordinate 26 # - y_io : cluster_io y coordinate 27 # - x_width : number of bits for x coordinate 28 # - y_width : number of bits for y coordinate 29 # - paddr_width : number of bits for physical address 31 # - nb_cmas : number of CMA channels 30 32 # - irq_per_proc : number of input IRQs per processor 31 # - use_ramdisk : use a ramdiskwhen True33 # - use_ramdisk : use a RAMDISK when True 32 34 # - peri_increment : address increment for replicated peripherals 33 35 # 34 # Regarding physical memory allocation, there is one allocator per cluster: 35 # - We use only one big physical page (2 Mbytes) for the five boot vsegs, 36 # allocated in cluster[0,0], identity mapping. 37 # - We use one big page per cluster for the kernel vsegs. 38 # The kernel_code, kernel_init and kernel_ptab can be replicated in all clusters. 39 # The kernel_data and kernel_uncdata shared vsegs are only mapped in cluster[0,0]. 40 # - We use 8 small physical pages (4 Kbytes) per cluster for the schedulers. 41 # - We use one big page for each external peripheral in IO cluster, 42 # - We use one small page per cluster for each internal peripheral. 43 ################################################################################### 36 # Regarding the boot and kernel vsegs mapping : 37 # - We use one big physical page (2 Mbytes) for the preloader and the four 38 # boot vsegs, all allocated in cluster[0,0]. 39 # - We use the 16 next big pages in cluster[0][0] to implement the RAMDISK. 40 # - We use one big page per cluster for the replicated kernel code vsegs. 41 # - We use one big page in cluster[0][0] for the kernel data vseg. 42 # - We use one big page per cluster for the distributed kernel heap vsegs. 43 # - We use one big page per cluster for the distributed ptab vsegs. 44 # - We use small physical pages (4 Kbytes) per cluster for the schedulers. 45 # - We use one big page for each external peripheral in IO cluster, 46 # - We use one small page per cluster for each internal peripheral. 47 ############################################################################### 44 48 45 49 ######################## 46 50 def arch( x_size = 2, 47 51 y_size = 2, 48 nb_procs = 2, 52 nb_procs = 4, 53 nb_ttys = 1, 49 54 fbf_width = 128 ): 50 55 51 56 ### define architecture constants 52 57 53 nb_ ttys = 154 nb_ nics = 255 x_io = 056 y_io = 058 nb_nics = 1 59 nb_cmas = 2 60 x_io = x_size - 1 61 y_io = y_size - 1 57 62 x_width = 4 58 63 y_width = 4 … … 60 65 paddr_width = 40 61 66 irq_per_proc = 4 62 use_ramdisk = True 63 peri_increment = 0x10000 # distributed peripherals vbase address increment 64 sched_increment = 0x10000 # distributed schedulers vbase address increment 65 ptab_increment = 0x200000 # distributed page tables vbase address increment 66 reset_address = 0x00000000 67 use_ramdisk = False 68 peri_increment = 0x10000 # distributed peripherals vbase increment 69 reset_address = 0x00000000 # wired preloader pbase address 67 70 68 71 ### parameters checking … … 70 73 assert( nb_procs <= (1 << p_width) ) 71 74 72 assert( (x_size >= 1) and (x_size <= 16) ) 73 74 assert( (y_size >= 1) and (y_size <= 16) ) 75 76 assert( nb_ttys == 1 ) 77 78 assert( ((x_io == 0) and (y_io == 0)) or 79 ((x_io == x_size-1) and (y_io == y_size-1)) ) 80 81 platform_name = 'tsar_leti_%d_%d_%d' % ( x_size, y_size, nb_procs ) 82 83 ### define physical segments 84 ### These segments are replicated in all clusters 85 86 ram_base = 0x0000000000 75 assert( x_size <= (1 << x_width) ) 76 77 assert( y_size <= (1 << y_width) ) 78 79 ### define type and name 80 81 platform_type = 'tsar_leti' 82 platform_name = '%s_%d_%d_%d' % (platform_type, x_size, y_size, nb_procs ) 83 84 ### define physical segments replicated in all clusters 85 ### the base address is extended by the cluster_xy (8 bits) 86 87 ram_base = 0x00000000 87 88 ram_size = 0x4000000 # 64 Mbytes 88 89 89 xcu_base = 0x 00F000000090 xcu_base = 0xF0000000 90 91 xcu_size = 0x1000 # 4 Kbytes 91 92 92 mmc_base = 0x 00E000000093 mmc_base = 0xF1000000 93 94 mmc_size = 0x1000 # 4 Kbytes 94 95 … … 96 97 ## These segments are only defined in cluster_io 97 98 98 offset_io= ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width)99 100 bdv_base = 0x 00F2000000 + offset_io99 cluster_xy = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) 100 101 bdv_base = 0xF2000000 + cluster_xy 101 102 bdv_size = 0x1000 # 4kbytes 102 103 103 tty_base = 0x 00F4000000 + offset_io104 tty_base = 0xF4000000 + cluster_xy 104 105 tty_size = 0x4000 # 16 Kbytes 105 106 106 nic_base = 0x 00F7000000 + offset_io107 nic_base = 0xF7000000 + cluster_xy 107 108 nic_size = 0x80000 # 512 kbytes 108 109 109 cma_base = 0x 00F8000000 + offset_io110 cma_base = 0xF8000000 + cluster_xy 110 111 cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics 111 112 112 fbf_base = 0x00F3000000 + offset_io 113 pic_base = 0xF9000000 + cluster_xy 114 pic_size = 0x1000 # 4 Kbytes 115 116 fbf_base = 0xF3000000 + cluster_xy 113 117 fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes 114 118 115 pic_base = 0x00F9000000 + offset_io116 pic_size = 0x1000 # 4 Kbytes117 118 rdk_base = 0x02000000119 rdk_size = 0x02000000 # 32 Mbytes120 119 121 120 ### define preloader & bootloader vsegs base addresses and sizes … … 133 132 134 133 boot_data_vbase = 0x000D0000 # ident 135 boot_data_size = 0x00080000 # 512 Kbytes 136 137 boot_stack_vbase = 0x00150000 # ident 138 boot_stack_size = 0x00050000 # 320 Kbytes 134 boot_data_size = 0x000C0000 # 768 Kbytes 135 136 boot_stack_vbase = 0x00190000 # ident 137 boot_stack_size = 0x00070000 # 448 Kbytes 138 139 ### define ramdisk vseg / must be identity mapping in cluster[0][0] 140 ### occupies 15 BPP after the boot 141 ramdisk_vbase = 0x00200000 142 ramdisk_size = 0x02000000 # 32 Mbytes 139 143 140 144 ### define kernel vsegs base addresses and sizes 141 ### code, init, ptab & sched vsegs are replicated in all clusters.145 ### code, init, ptab, heap & sched vsegs are replicated in all clusters. 142 146 ### data & uncdata vsegs are only mapped in cluster[0][0]. 143 ### - We pack code, init, data vsegs in the same BIG page.144 ### - We use another BIG page for the ptab vseg.145 ### - We use 2*nb_procs SMALL pages for the sched vseg.146 ### - we use one SMALL page for uncdata147 ### => kernel cost is 2 BPPs and (2*n + 1) SPPs per cluster.148 147 149 148 kernel_code_vbase = 0x80000000 150 kernel_code_size = 0x00080000 # 512 Kbytes per cluster 151 152 kernel_init_vbase = 0x80080000 153 kernel_init_size = 0x00080000 # 512 Kbytes per cluster 154 155 kernel_data_vbase = 0x80100000 156 kernel_data_size = 0x00100000 # 1 Mbytes in cluster[0][0] 157 158 kernel_uncdata_vbase = 0x80200000 159 kernel_uncdata_size = 0x00001000 # 4 Kbytes 160 161 kernel_sched_vbase = 0x80400000 # distributed in all clusters 162 kernel_sched_size = 0x00002000 * nb_procs # 8 kbytes per processor 163 164 kernel_ptab_vbase = 0xC0000000 149 kernel_code_size = 0x00100000 # 1 Mbytes per cluster 150 151 kernel_init_vbase = 0x80100000 152 kernel_init_size = 0x00100000 # 1 Mbytes per cluster 153 154 kernel_data_vbase = 0x90000000 155 kernel_data_size = 0x00200000 # 2 Mbytes in cluster[0][0] 156 157 kernel_uncdata_vbase = 0x90200000 158 kernel_uncdata_size = 0x00001000 # 4 Kbytes in cluster[0][0] 159 160 kernel_ptab_vbase = 0xE0000000 165 161 kernel_ptab_size = 0x00200000 # 2 Mbytes per cluster 166 162 163 kernel_heap_vbase = 0xD0000000 164 kernel_heap_size = 0x00200000 # 2 Mbytes per cluster 165 166 kernel_sched_vbase = 0xA0000000 167 kernel_sched_size = 0x00002000 * nb_procs # 8 kbytes per proc per cluster 168 169 ##################### 167 170 ### create mapping 171 ##################### 168 172 169 173 mapping = Mapping( name = platform_name, 174 p_type = platform_type, 170 175 x_size = x_size, 171 176 y_size = y_size, … … 185 190 ram_size = ram_size ) 186 191 187 ### external peripherals (accessible in cluster[0,0] only for this mapping) 188 189 bdv = mapping.addPeriph( 'BDV', base = bdv_base, size = bdv_size, ptype = 'IOC', subtype = 'BDV' ) 190 191 tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) 192 193 if x_io != 0 or y_io != 0: 194 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 195 cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) 196 fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = fbf_width ) 197 pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, ptype = 'PIC', channels = 32 ) 198 199 mapping.addIrq( pic, index = 0 , isrtype = 'ISR_NIC_RX', channel = 0 ) 200 mapping.addIrq( pic, index = 1 , isrtype = 'ISR_NIC_RX', channel = 1 ) 201 mapping.addIrq( pic, index = 2 , isrtype = 'ISR_NIC_TX', channel = 0 ) 202 mapping.addIrq( pic, index = 3 , isrtype = 'ISR_NIC_TX', channel = 1 ) 203 mapping.addIrq( pic, index = 4 , isrtype = 'ISR_CMA' , channel = 0 ) 204 mapping.addIrq( pic, index = 5 , isrtype = 'ISR_CMA' , channel = 1 ) 205 mapping.addIrq( pic, index = 6 , isrtype = 'ISR_CMA' , channel = 2 ) 206 mapping.addIrq( pic, index = 7 , isrtype = 'ISR_CMA' , channel = 3 ) 207 mapping.addIrq( pic, index = 8 , isrtype = 'ISR_BDV' , channel = 0 ) 208 mapping.addIrq( pic, index = 16, isrtype = 'ISR_TTY_RX', channel = 0 ) 209 210 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 211 vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', 212 local = False, big = True ) 213 214 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 215 vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', 216 local = False, big = True ) 217 218 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 219 vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', 220 local = False, big = True ) 221 222 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 223 vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', 224 local = False, big = True ) 225 226 ### hardware components replicated in all clusters 192 ########################### 193 ### Hardware Description 194 ########################### 227 195 228 196 for x in xrange( x_size ): … … 230 198 cluster_xy = (x << y_width) + y; 231 199 offset = cluster_xy << (paddr_width - x_width - y_width) 232 233 ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) 234 235 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 236 ptype = 'MMC' ) 237 238 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 239 ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) 240 241 # IRQs replicated in all clusters 242 mapping.addIrq( xcu, index = 8, isrtype = 'ISR_MMC' ) 243 244 # IRQ in IO cluster (0,0) 245 if x == 0 and y == 0: 246 mapping.addIrq( xcu, index = 9 , isrtype = 'ISR_BDV' ) 247 mapping.addIrq( xcu, index = 10, isrtype = 'ISR_TTY_RX' ) 248 249 # processors 250 for p in xrange ( nb_procs ): 251 mapping.addProc( x, y, p ) 252 253 ### global vsegs for preloader & boot_loader 200 201 ### components replicated in all clusters but the upper row 202 if ( y < (y_size - 1) ): 203 204 ram = mapping.addRam( 'RAM', base = ram_base + offset, 205 size = ram_size ) 206 207 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, 208 size = mmc_size, ptype = 'MMC' ) 209 210 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, 211 size = xcu_size, ptype = 'XCU', 212 channels = nb_procs * irq_per_proc, arg = 16 ) 213 214 mapping.addIrq( xcu, index = 8, isrtype = 'ISR_MMC' ) 215 216 for p in xrange ( nb_procs ): 217 mapping.addProc( x, y, p ) 218 219 ### external peripherals in cluster_io 220 if ( (x==x_io) and (y==y_io) ): 221 222 bdv = mapping.addPeriph( 'BDV', base = bdv_base, size = bdv_size, 223 ptype = 'IOC', subtype = 'BDV' ) 224 225 tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, 226 ptype = 'TTY', channels = nb_ttys ) 227 228 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, 229 ptype = 'NIC', channels = nb_nics ) 230 231 cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, 232 ptype = 'CMA', channels = nb_cmas ) 233 234 fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, 235 ptype = 'FBF', arg = fbf_width ) 236 237 pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, 238 ptype = 'PIC', channels = 32 ) 239 240 mapping.addIrq( pic, index = 0 , isrtype = 'ISR_NIC_RX', channel = 0 ) 241 mapping.addIrq( pic, index = 1 , isrtype = 'ISR_NIC_RX', channel = 1 ) 242 243 mapping.addIrq( pic, index = 2 , isrtype = 'ISR_NIC_TX', channel = 0 ) 244 mapping.addIrq( pic, index = 3 , isrtype = 'ISR_NIC_TX', channel = 1 ) 245 246 mapping.addIrq( pic, index = 4 , isrtype = 'ISR_CMA' , channel = 0 ) 247 mapping.addIrq( pic, index = 5 , isrtype = 'ISR_CMA' , channel = 1 ) 248 mapping.addIrq( pic, index = 6 , isrtype = 'ISR_CMA' , channel = 2 ) 249 mapping.addIrq( pic, index = 7 , isrtype = 'ISR_CMA' , channel = 3 ) 250 251 mapping.addIrq( pic, index = 8 , isrtype = 'ISR_BDV' , channel = 0 ) 252 253 mapping.addIrq( pic, index = 16, isrtype = 'ISR_TTY_RX', channel = 0 ) 254 mapping.addIrq( pic, index = 17, isrtype = 'ISR_TTY_RX', channel = 1 ) 255 mapping.addIrq( pic, index = 18, isrtype = 'ISR_TTY_RX', channel = 2 ) 256 mapping.addIrq( pic, index = 19, isrtype = 'ISR_TTY_RX', channel = 3 ) 257 mapping.addIrq( pic, index = 20, isrtype = 'ISR_TTY_RX', channel = 4 ) 258 mapping.addIrq( pic, index = 21, isrtype = 'ISR_TTY_RX', channel = 5 ) 259 mapping.addIrq( pic, index = 22, isrtype = 'ISR_TTY_RX', channel = 6 ) 260 mapping.addIrq( pic, index = 23, isrtype = 'ISR_TTY_RX', channel = 7 ) 261 262 ################################### 263 ### boot & kernel vsegs mapping 264 ################################### 265 266 ### global vsegs for preloader & boot_loader are mapped in cluster[0][0] 254 267 ### we want to pack those 5 vsegs in the same big page 255 268 ### => same flags CXW_ / identity mapping / non local / big page … … 275 288 identity = True, local = False, big = True ) 276 289 290 ### global vseg for RAM-DISK in cluster[0][0] 291 ### identity mapping / non local / big pages 292 if use_ramdisk: 293 294 mapping.addGlobal( 'seg_ramdisk', ramdisk_vbase, ramdisk_size, 295 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 296 identity = True, local = True, big = True ) 297 277 298 ### global vsegs kernel_code, kernel_init : local / big page 278 ### replicated in all clusters with the same name (same vbase) 279 for x in xrange( x_size ): 280 for y in xrange( y_size ): 281 mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size, 299 ### replicated in all clusters containing processors 300 ### same content => same name / same vbase 301 for x in xrange( x_size ): 302 for y in xrange( y_size - 1 ): 303 304 mapping.addGlobal( 'seg_kernel_code', 305 kernel_code_vbase, kernel_code_size, 282 306 'CXW_', vtype = 'ELF', x = x, y = y, pseg = 'RAM', 283 307 binpath = 'build/kernel/kernel.elf', 284 308 local = True, big = True ) 285 309 286 mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size, 310 mapping.addGlobal( 'seg_kernel_init', 311 kernel_init_vbase, kernel_init_size, 287 312 'CXW_', vtype = 'ELF', x = x, y = y, pseg = 'RAM', 288 313 binpath = 'build/kernel/kernel.elf', … … 291 316 ### global vseg kernel_data: non local / big page 292 317 ### Only mapped in cluster[0][0] 293 mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, 294 'CXW_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 295 binpath = 'build/kernel/kernel.elf', 318 mapping.addGlobal( 'seg_kernel_data', 319 kernel_data_vbase, kernel_data_size, 320 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 321 binpath = 'build/kernel/kernel.elf', 296 322 local = False, big = True ) 297 323 298 324 ### global vseg kernel_uncdata: non local / small page 299 325 ### Only mapped in cluster[0][0] 300 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, 326 mapping.addGlobal( 'seg_kernel_uncdata', 327 kernel_uncdata_vbase, kernel_uncdata_size, 301 328 '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 302 binpath = 'build/kernel/kernel.elf', 329 binpath = 'build/kernel/kernel.elf', 303 330 local = False, big = False ) 304 331 305 for x in xrange( x_size ):306 for y in xrange( y_size ):307 cluster_xy = (x << y_width) + y;308 309 ### Global vsegs kernel_ptab_x_y: non local / big pages310 ### replicated in all clusters with name indexed by (x,y)311 ### as vbase address is incremented by (cluster_xy * vseg_increment) 312 offset = cluster_xy * ptab_increment313 mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y),kernel_ptab_vbase + offset, kernel_ptab_size,332 ### Global vsegs kernel_ptab_x_y: non local / big page 333 ### replicated in all clusters containing processors 334 ### different content => name & vbase indexed by (x,y) 335 for x in xrange( x_size ): 336 for y in xrange( y_size - 1 ): 337 offset = ((x << y_width) + y) * kernel_ptab_size 338 339 mapping.addGlobal( 'seg_kernel_ptab_%d_%d' %(x,y), 340 kernel_ptab_vbase + offset, kernel_ptab_size, 314 341 'CXW_', vtype = 'PTAB', x = x, y = y, pseg = 'RAM', 315 342 local = False, big = True ) 316 343 317 ### global vsegs kernel_sched : non local / small pages 318 ### allocated in all clusters with name indexed by (x,y) 319 ### as vbase address is incremented by (cluster_xy * vseg_increment) 320 offset = cluster_xy * sched_increment 321 mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y), kernel_sched_vbase + offset, kernel_sched_size, 344 ### global vsegs kernel_sched : non local / small pages 345 ### allocated in all clusters containing processors 346 ### different content => name & vbase indexed by (x,y) 347 for x in xrange( x_size ): 348 for y in xrange( y_size - 1 ): 349 offset = ((x << y_width) + y) * kernel_ptab_size 350 351 mapping.addGlobal( 'seg_kernel_sched_%d_%d' %(x,y), 352 kernel_sched_vbase + offset , kernel_sched_size, 322 353 'C_W_', vtype = 'SCHED', x = x, y = y, pseg = 'RAM', 323 354 local = False, big = False ) 324 355 325 ### global vseg for ram disk 326 if use_ramdisk: 327 mapping.addGlobal( 'seg_rdk', rdk_base, rdk_size, '__W_', 328 vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 329 identity = True, local = False, big = True ) 356 ### global vsegs kernel_heap_x_y : non local / big pages 357 ### distributed in all clusters containing processors 358 ### different content => name & vbase indexed by (x,y) 359 for x in xrange( x_size ): 360 for y in xrange( y_size - 1 ): 361 offset = ((x << y_width) + y) * kernel_heap_size 362 363 mapping.addGlobal( 'seg_kernel_heap_%d_%d' %(x,y), 364 kernel_heap_vbase + offset , kernel_heap_size, 365 'C_W_', vtype = 'HEAP', x = x , y = y , pseg = 'RAM', 366 local = False, big = True ) 330 367 331 368 ### global vsegs for external peripherals: non local / big page 332 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 333 vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', 334 local = False, big = True ) 335 336 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 337 vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', 369 ### only mapped in cluster_io 370 mapping.addGlobal( 'seg_bdv', 371 bdv_base, bdv_size, 372 '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'BDV', 373 local = False, big = True ) 374 375 mapping.addGlobal( 'seg_tty', 376 tty_base, tty_size, 377 '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'TTY', 378 local = False, big = True ) 379 380 mapping.addGlobal( 'seg_nic', 381 nic_base, nic_size, 382 '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'NIC', 383 local = False, big = True ) 384 385 mapping.addGlobal( 'seg_cma', 386 cma_base, cma_size, 387 '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'CMA', 388 local = False, big = True ) 389 390 mapping.addGlobal( 'seg_fbf', 391 fbf_base, fbf_size, 392 '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'FBF', 393 local = False, big = True ) 394 395 mapping.addGlobal( 'seg_pic', 396 pic_base, pic_size, 397 '__W_', vtype = 'PERI', x = x_io, y = y_io, pseg = 'PIC', 338 398 local = False, big = True ) 339 399 340 400 ### global vsegs for internal peripherals : non local / small pages 341 ### allocated in all clusters with name indexed by (x,y)342 ### as vbase address is incremented by (cluster_xy * vseg_increment)343 for x in xrange( x_size ): 344 for y in xrange( y_size ):401 ### allocated in all clusters containing processors 402 ### name and vbase indexed by (x,y) 403 for x in xrange( x_size ): 404 for y in xrange( y_size - 1 ): 345 405 offset = ((x << y_width) + y) * peri_increment 346 406 347 mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, 407 mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), 408 xcu_base + offset, xcu_size, 348 409 '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU', 349 410 local = False, big = False ) 350 411 351 mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, 412 mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), 413 mmc_base + offset, mmc_size, 352 414 '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC', 353 415 local = False, big = False ) 354 416 355 ### return mapping ###356 357 417 return mapping 358 418 359 ########################## ####### platform test #######################################################419 ########################## platform test ############################################# 360 420 361 421 if __name__ == '__main__': -
trunk/platforms/tsar_generic_leti/top.cpp
r897 r937 3 3 // Author: Alain Greiner 4 4 // Copyright: UPMC/LIP6 5 // Date : february 201 45 // Date : february 2013 / updated january 2015 6 6 // This program is released under the GNU public license 7 7 ///////////////////////////////////////////////////////////////////////// … … 13 13 // (this is defined in the tsar_xbar_cluster). 14 14 // 15 // It does not use an external ROM, as the boot code is (pre)loaded 16 // in cluster (0,0) memory at address 0x0. 15 // The main hardware parameters are the mesh size (X_SIZE & Y_SIZE), 16 // and the number of processors per cluster (NB_PROCS_MAX). 17 // The NB_PROCS_MAX parameter cannot be larger than 4. 18 // 19 // All external peripherals are located in cluster[X_SIZE-1][Y_SIZE-1], 20 // and are connected to an IO bus (implemented as a vci_local_crossbar): 21 // - one disk controller 22 // - one multi-channel ethernet controller 23 // - one multi-channel chained buffer dma controller 24 // - one multi-channel tty controller 25 // - one frame buffer controller 26 // - one iopic controller 27 // This IO bus is directly connected to the north ports of the CMD/RSP 28 // routers in cluster[X_SIZE-1][y_SIZE-2] through VCI/DSPIN wrappers. 29 // All other clusters in the upper row are empty: no processors, 30 // no ram, no routers. 31 // The X_SIZE parameter must be larger than 0, but no larger than 16. 32 // The Y_SIZE parameter must be larger than 1, but no larger than 16. 33 // 34 // We don't use an external ROM, as the boot code is (pre)loaded 35 // in RAM in cluster[0][0] at address 0x0. 36 // 37 // An optional RAMDISK of 32 Mbytes can be used in RAM of cluster[0][0]. 17 38 // 18 39 // The physical address space is 40 bits. 19 40 // The 8 address MSB bits define the cluster index. 20 41 // 21 // The main hardware parameters are the mesh size (X_SIZE & Y_SIZE), 22 // and the number of processors per cluster (NB_PROCS_MAX). 23 // The number of clusters cannot be larger than 128. 24 // The number of processors per cluster cannot be larger than 4. 25 // 26 // Each cluster contains: 27 // - 5 dspin_local_crossbar (local interconnect) 28 // - 5 dspin_router (global interconnect) 29 // - up to 4 vci_cc_vcache wrapping a MIPS32 processor 42 // Besides the processors, each cluster contains: 43 // - 5 L1/L2 DSPIN routers implementing 5 separated NOCs 30 44 // - 1 vci_mem_cache 31 45 // - 1 vci_xicu 32 // - 1 vci_simple_ram (to modelthe L3 cache).46 // - 1 vci_simple_ram (to emulate the L3 cache). 33 47 // 34 48 // Each processor receives 4 consecutive IRQ lines from the local XICU. … … 36 50 // In all clusters, the MEMC IRQ line (signaling a late write error) 37 51 // is connected to XICU HWI[8] 38 // The cluster (0,0) contains two "backup" peripherals:39 // - one block device controller, whose IRQ is connected to XICU HWI[9].40 // - one single channel TTY controller, whose IRQ is connected to XICU HWI[10].41 //42 // The cluster internal architecture is defined in file tsar_leti_cluster,43 // that must be considered as an extension of this top.cpp file.44 //45 // Besides the hardware components in clusters, "external" peripherals46 // are connected to an external IO bus (implemented as a vci_local_crossbar):47 // - one disk controller48 // - one multi-channel ethernet controller49 // - one multi-channel chained buffer dma controller50 // - one multi-channel tty controller51 // - one frame buffer controller52 // - one 32 channels iopic controller53 52 // 54 53 // This IOBUS is connected to the north port of the DIR_CMD … … 63 62 // - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]] 64 63 // - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]] 64 // 65 // The cluster internal architecture is defined in file tsar_leti_cluster, 66 // that must be considered as an extension of this top.cpp file. 65 67 //////////////////////////////////////////////////////////////////////////// 66 68 // The following parameters must be defined in the hard_config.h file : … … 73 75 // - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max) 74 76 // - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max) 77 // - FBUF_X_SIZE : number of pixels per line for frame buffer 78 // - FBUF_Y_SIZE : number of lines for frame buffer 75 79 // 76 80 // Some other hardware parameters are not used when compiling the OS, 77 81 // and are only defined in this top.cpp file: 78 82 // - XRAM_LATENCY : external ram latency 79 // - MEMC_WAYS : L2 cache number of ways80 // - MEMC_SETS : L2 cache number of sets81 83 // - L1_IWAYS : L1 cache instruction number of ways 82 84 // - L1_ISETS : L1 cache instruction number of sets 83 85 // - L1_DWAYS : L1 cache data number of ways 84 86 // - L1_DSETS : L1 cache data number of sets 85 // - FBUF_X_SIZE : width of frame buffer (pixels) 86 // - FBUF_Y_SIZE : heigth of frame buffer (lines) 87 // - BDEV_IMAGE_NAME : file pathname for block device 88 // - NIC_RX_NAME : file pathname for NIC received packets 89 // - NIC_TX_NAME : file pathname for NIC transmited packets 90 // - NIC_MAC4 : MAC address 91 // - NIC_MAC2 : MAC address 87 // - BDEV_IMAGE_NAME : pathname for block device disk image 92 88 ///////////////////////////////////////////////////////////////////////// 93 89 // General policy for 40 bits physical address decoding: … … 168 164 169 165 170 /////////////////////////////////////////////////////////////////////////////////////// //166 /////////////////////////////////////////////////////////////////////////////////////// 171 167 // Secondary Hardware Parameters 172 ///////////////////////////////////////////////////////////////////////////////////////// 173 174 #define MAX_TTY_CHANNELS 8 175 #define MAX_CMA_CHANNELS 4 176 #define MAX_NIC_CHANNELS 2 168 /////////////////////////////////////////////////////////////////////////////////////// 169 170 #define XMAX X_SIZE // actual number of columns in 2D mesh 171 #define YMAX (Y_SIZE - 1) // actual number of rows in 2D mesh 177 172 178 173 #define XRAM_LATENCY 0 … … 187 182 #define L1_DSETS 64 188 183 189 #define NIC_MAC4 0XBABEF00D 190 #define NIC_MAC2 0xBEEF 191 #define NIC_RX_NAME "/dev/null" 192 #define NIC_TX_NAME "/dev/null" 184 #define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" 185 186 #define ROM_SOFT_NAME "../../softs/tsar_boot/preloader.elf" 193 187 194 188 #define NORTH 0 … … 230 224 using namespace soclib::common; 231 225 232 uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles233 size_t threads = 1; // simulator's threads number234 bool trace_ok = false; // trace activated235 uint32_t trace_from = 0; // trace start cycle236 bool trace_proc_ok = false; // detailed proc trace activated237 size_t trace_memc_ok = false; // detailed memc trace activated238 size_t trace_memc_id = 0; // index of memc to be traced239 size_t trace_proc_id = 0; // index of proc to be traced240 uint32_t frozen_cycles = MAX_FROZEN_CYCLES;241 char soft_name[256] = "soft.elf";242 char disk_name[256] = "disk.img";226 uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles 227 size_t threads = 1; // simulator's threads number 228 bool trace_ok = false; // trace activated 229 uint32_t trace_from = 0; // trace start cycle 230 bool trace_proc_ok = false; // detailed proc trace activated 231 size_t trace_memc_ok = false; // detailed memc trace activated 232 size_t trace_memc_id = 0; // index of memc to be traced 233 size_t trace_proc_id = 0; // index of proc to be traced 234 char soft_name[256] = ROM_SOFT_NAME; // pathname for ROM binary code 235 char disk_name[256] = BDEV_IMAGE_NAME; // pathname for DISK image 236 uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // for debug 243 237 struct timeval t1,t2; 244 238 uint64_t ms1,ms2; … … 265 259 size_t y = trace_memc_id & ((1<<Y_WIDTH)-1); 266 260 267 assert( (x < X _SIZE) and (y < (Y_SIZE)) and261 assert( (x < XMAX) and (y < (YMAX)) and 268 262 "MEMCID parameter refers a not valid memory cache"); 269 263 } … … 277 271 size_t l = trace_proc_id & ((1<<P_WIDTH)-1) ; 278 272 279 assert( (x < X _SIZE) and (y < Y_SIZE) and (l < NB_PROCS_MAX) and273 assert( (x < XMAX) and (y < YMAX) and (l < NB_PROCS_MAX) and 280 274 "PROCID parameter refers a not valid processor"); 281 275 } 282 else if ((strcmp(argv[n], "- SOFT") == 0) && ((n + 1) < argc))276 else if ((strcmp(argv[n], "-ROM") == 0) && ((n + 1) < argc)) 283 277 { 284 278 strcpy(soft_name, argv[n + 1]); … … 302 296 std::cout << " The order is not important." << std::endl; 303 297 std::cout << " Accepted arguments are :" << std::endl << std::endl; 304 std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl;305 std::cout << " - DEBUG debug_start_cycle" << std::endl;306 std::cout << " - SOFT path to soft" << std::endl;307 std::cout << " - DISK path to disk image" << std::endl;308 std::cout << " - THREADS simulator's threads number" << std::endl;309 std::cout << " - FROZEN max_number_of_lines" << std::endl;310 std::cout << " - PERIOD number_of_cycles between trace" << std::endl;311 std::cout << " - MEMCID index_memc_to_be_traced" << std::endl;312 std::cout << " - PROCID index_proc_to_be_traced" << std::endl;298 std::cout << " - NCYCLES number_of_simulated_cycles" << std::endl; 299 std::cout << " - DEBUG debug_start_cycle" << std::endl; 300 std::cout << " - ROM path to ROM image" << std::endl; 301 std::cout << " - DISK path to disk image" << std::endl; 302 std::cout << " - THREADS simulator's threads number" << std::endl; 303 std::cout << " - FROZEN max_number_of_lines" << std::endl; 304 std::cout << " - PERIOD number_of_cycles between trace" << std::endl; 305 std::cout << " - MEMCID index_memc_to_be_traced" << std::endl; 306 std::cout << " - PROCID index_proc_to_be_traced" << std::endl; 313 307 exit(0); 314 308 } … … 317 311 318 312 // checking hardware parameters 319 assert( ((X_SIZE==1) or (X_SIZE==2) or (X_SIZE==4) or (X_SIZE==8) or 320 (X_SIZE==16)) and 313 assert( ((X_SIZE <= 16) and (X_SIZE > 0)) and 321 314 "Illegal X_SIZE parameter" ); 322 315 323 assert( ((Y_SIZE ==1) or (Y_SIZE==2) or (Y_SIZE==4) or (Y_SIZE==8)) and316 assert( ((Y_SIZE <= 16) and (Y_SIZE > 1)) and 324 317 "Illegal Y_SIZE parameter" ); 325 318 … … 330 323 "Illegal NB_PROCS_MAX parameter" ); 331 324 332 assert( (NB_CMA_CHANNELS <= MAX_CMA_CHANNELS) and325 assert( (NB_CMA_CHANNELS <= 4) and 333 326 "The NB_CMA_CHANNELS parameter cannot be larger than 4" ); 334 327 335 assert( (NB_TTY_CHANNELS <= MAX_TTY_CHANNELS) and336 "The NB_TTY_CHANNELS parameter cannot be larger than 8" );337 338 assert( (NB_NIC_CHANNELS <= MAX_NIC_CHANNELS) and328 assert( (NB_TTY_CHANNELS <= 8) and 329 "The NB_TTY_CHANNELS parameter cannot be larger than 16" ); 330 331 assert( (NB_NIC_CHANNELS <= 2) and 339 332 "The NB_NIC_CHANNELS parameter cannot be larger than 2" ); 340 333 … … 343 336 344 337 assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and 345 " ERROR: you must have X_WIDTH == Y_WIDTH == 4");338 "You must have X_WIDTH == Y_WIDTH == 4"); 346 339 347 340 std::cout << std::endl; 348 341 349 std::cout << " - X _SIZE = " << X_SIZE<< std::endl;350 std::cout << " - Y _SIZE = " << Y_SIZE<< std::endl;342 std::cout << " - XMAX = " << XMAX << std::endl; 343 std::cout << " - YMAX = " << YMAX << std::endl; 351 344 std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; 352 std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl;353 345 std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; 354 346 std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; 347 std::cout << " - NB_CMA_CHANNELS = " << NB_CMA_CHANNELS << std::endl; 355 348 std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; 356 349 std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; … … 405 398 406 399 // replicated segments 407 for (size_t x = 0; x < X _SIZE; x++)400 for (size_t x = 0; x < XMAX; x++) 408 401 { 409 for (size_t y = 0; y < (Y _SIZE) ; y++)402 for (size_t y = 0; y < (YMAX) ; y++) 410 403 { 411 404 sc_uint<vci_address_width> offset; … … 436 429 IntTab(cluster(0,0),BDEV_TGTID), false)); 437 430 438 // segments for peripherals in cluster_io (X _SIZE-1,Y_SIZE)431 // segments for peripherals in cluster_io (XMAX-1,YMAX) 439 432 sc_uint<vci_address_width> offset; 440 offset = ((sc_uint<vci_address_width>)cluster(X _SIZE-1,Y_SIZE)) << 32;433 offset = ((sc_uint<vci_address_width>)cluster(XMAX-1,YMAX)) << 32; 441 434 442 435 maptabd.add(Segment("seg_mtty", SEG_TTY_BASE + offset, SEG_TTY_SIZE, 443 IntTab(cluster(X _SIZE-1, Y_SIZE),MTTY_TGTID), false));436 IntTab(cluster(XMAX-1, YMAX),MTTY_TGTID), false)); 444 437 445 438 maptabd.add(Segment("seg_fbuf", SEG_FBF_BASE + offset, SEG_FBF_SIZE, 446 IntTab(cluster(X _SIZE-1, Y_SIZE),FBUF_TGTID), false));439 IntTab(cluster(XMAX-1, YMAX),FBUF_TGTID), false)); 447 440 448 441 maptabd.add(Segment("seg_bdev", SEG_IOC_BASE + offset, SEG_IOC_SIZE, 449 IntTab(cluster(X _SIZE-1, Y_SIZE),BDEV_TGTID), false));442 IntTab(cluster(XMAX-1, YMAX),BDEV_TGTID), false)); 450 443 451 444 maptabd.add(Segment("seg_mnic", SEG_NIC_BASE + offset, SEG_NIC_SIZE, 452 IntTab(cluster(X _SIZE-1, Y_SIZE),MNIC_TGTID), false));445 IntTab(cluster(XMAX-1, YMAX),MNIC_TGTID), false)); 453 446 454 447 maptabd.add(Segment("seg_cdma", SEG_CMA_BASE + offset, SEG_CMA_SIZE, 455 IntTab(cluster(X _SIZE-1, Y_SIZE),CDMA_TGTID), false));448 IntTab(cluster(XMAX-1, YMAX),CDMA_TGTID), false)); 456 449 457 450 maptabd.add(Segment("seg_iopi", SEG_PIC_BASE + offset, SEG_PIC_SIZE, 458 IntTab(cluster(X _SIZE-1, Y_SIZE),IOPI_TGTID), false));451 IntTab(cluster(XMAX-1, YMAX),IOPI_TGTID), false)); 459 452 460 453 std::cout << maptabd << std::endl; … … 469 462 0x00FF000000ULL); 470 463 471 for (size_t x = 0; x < X _SIZE; x++)472 { 473 for (size_t y = 0; y < (Y _SIZE) ; y++)464 for (size_t x = 0; x < XMAX; x++) 465 { 466 for (size_t y = 0; y < (YMAX) ; y++) 474 467 { 475 468 sc_uint<vci_address_width> offset; … … 498 491 sc_signal<bool> signal_irq_mnic_tx[NB_NIC_CHANNELS]; 499 492 sc_signal<bool> signal_irq_mtty_rx[NB_TTY_CHANNELS]; 500 // sc_signal<bool> signal_irq_mtty_tx[NB_TTY_CHANNELS];501 493 sc_signal<bool> signal_irq_cdma[NB_CMA_CHANNELS]; 502 494 sc_signal<bool> signal_irq_false; … … 504 496 // Horizontal inter-clusters DSPIN signals 505 497 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_inc = 506 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", X _SIZE-1, Y_SIZE);498 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_inc", XMAX-1, YMAX); 507 499 DspinSignals<dspin_cmd_width>** signal_dspin_h_cmd_dec = 508 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", X _SIZE-1, Y_SIZE);500 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cmd_dec", XMAX-1, YMAX); 509 501 510 502 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_inc = 511 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", X _SIZE-1, Y_SIZE);503 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_inc", XMAX-1, YMAX); 512 504 DspinSignals<dspin_rsp_width>** signal_dspin_h_rsp_dec = 513 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", X _SIZE-1, Y_SIZE);505 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_rsp_dec", XMAX-1, YMAX); 514 506 515 507 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_inc = 516 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", X _SIZE-1, Y_SIZE);508 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_inc", XMAX-1, YMAX); 517 509 DspinSignals<dspin_cmd_width>** signal_dspin_h_m2p_dec = 518 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", X _SIZE-1, Y_SIZE);510 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_m2p_dec", XMAX-1, YMAX); 519 511 520 512 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_inc = 521 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", X _SIZE-1, Y_SIZE);513 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_inc", XMAX-1, YMAX); 522 514 DspinSignals<dspin_rsp_width>** signal_dspin_h_p2m_dec = 523 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", X _SIZE-1, Y_SIZE);515 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_h_p2m_dec", XMAX-1, YMAX); 524 516 525 517 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_inc = 526 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", X _SIZE-1, Y_SIZE);518 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_inc", XMAX-1, YMAX); 527 519 DspinSignals<dspin_cmd_width>** signal_dspin_h_cla_dec = 528 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", X _SIZE-1, Y_SIZE);520 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_h_cla_dec", XMAX-1, YMAX); 529 521 530 522 // Vertical inter-clusters DSPIN signals 531 523 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_inc = 532 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", X _SIZE, Y_SIZE-1);524 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_inc", XMAX, YMAX-1); 533 525 DspinSignals<dspin_cmd_width>** signal_dspin_v_cmd_dec = 534 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", X _SIZE, Y_SIZE-1);526 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cmd_dec", XMAX, YMAX-1); 535 527 536 528 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_inc = 537 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", X _SIZE, Y_SIZE-1);529 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_inc", XMAX, YMAX-1); 538 530 DspinSignals<dspin_rsp_width>** signal_dspin_v_rsp_dec = 539 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", X _SIZE, Y_SIZE-1);531 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_rsp_dec", XMAX, YMAX-1); 540 532 541 533 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_inc = 542 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", X _SIZE, Y_SIZE-1);534 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_inc", XMAX, YMAX-1); 543 535 DspinSignals<dspin_cmd_width>** signal_dspin_v_m2p_dec = 544 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", X _SIZE, Y_SIZE-1);536 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_m2p_dec", XMAX, YMAX-1); 545 537 546 538 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_inc = 547 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", X _SIZE, Y_SIZE-1);539 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_inc", XMAX, YMAX-1); 548 540 DspinSignals<dspin_rsp_width>** signal_dspin_v_p2m_dec = 549 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", X _SIZE, Y_SIZE-1);541 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_v_p2m_dec", XMAX, YMAX-1); 550 542 551 543 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_inc = 552 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", X _SIZE, Y_SIZE-1);544 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_inc", XMAX, YMAX-1); 553 545 DspinSignals<dspin_cmd_width>** signal_dspin_v_cla_dec = 554 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", X _SIZE, Y_SIZE-1);546 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_v_cla_dec", XMAX, YMAX-1); 555 547 556 548 // Mesh boundaries DSPIN signals (Most of those signals are not used...) 557 549 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_in = 558 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , X _SIZE, Y_SIZE, 4);550 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_in" , XMAX, YMAX, 4); 559 551 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cmd_out = 560 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", X _SIZE, Y_SIZE, 4);552 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cmd_out", XMAX, YMAX, 4); 561 553 562 554 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_in = 563 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , X _SIZE, Y_SIZE, 4);555 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_in" , XMAX, YMAX, 4); 564 556 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_rsp_out = 565 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", X _SIZE, Y_SIZE, 4);557 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_rsp_out", XMAX, YMAX, 4); 566 558 567 559 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_in = 568 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , X _SIZE, Y_SIZE, 4);560 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_in" , XMAX, YMAX, 4); 569 561 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_m2p_out = 570 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", X _SIZE, Y_SIZE, 4);562 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_m2p_out", XMAX, YMAX, 4); 571 563 572 564 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_in = 573 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , X _SIZE, Y_SIZE, 4);565 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_in" , XMAX, YMAX, 4); 574 566 DspinSignals<dspin_rsp_width>*** signal_dspin_bound_p2m_out = 575 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", X _SIZE, Y_SIZE, 4);567 alloc_elems<DspinSignals<dspin_rsp_width> >("signal_dspin_bound_p2m_out", XMAX, YMAX, 4); 576 568 577 569 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_in = 578 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , X _SIZE, Y_SIZE, 4);570 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_in" , XMAX, YMAX, 4); 579 571 DspinSignals<dspin_cmd_width>*** signal_dspin_bound_cla_out = 580 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", X _SIZE, Y_SIZE, 4);572 alloc_elems<DspinSignals<dspin_cmd_width> >("signal_dspin_bound_cla_out", XMAX, YMAX, 4); 581 573 582 574 // VCI signals for iobus and peripherals … … 611 603 soclib::common::Loader loader( soft_name ); 612 604 #endif 605 613 606 loader.memory_default(0xAA); 614 615 ///////////////////////////616 // processor iss617 ///////////////////////////618 607 619 608 typedef soclib::common::GdbServer<soclib::common::Mips32ElIss> proc_iss; … … 621 610 622 611 ////////////////////////////////////////////////////////////// 623 // mesh construction: only (X_SIZE) * (Y_SIZE)clusters612 // mesh construction: XMAX * YMAX clusters 624 613 ////////////////////////////////////////////////////////////// 625 614 … … 627 616 dspin_rsp_width, 628 617 vci_param_int, 629 vci_param_ext>* clusters[X _SIZE][Y_SIZE];618 vci_param_ext>* clusters[XMAX][YMAX]; 630 619 631 620 #if USE_OPENMP … … 634 623 #pragma omp for 635 624 #endif 636 for (size_t i = 0; i < (X _SIZE * (Y_SIZE)); i++)625 for (size_t i = 0; i < (XMAX * YMAX); i++) 637 626 { 638 size_t x = i / (Y _SIZE);639 size_t y = i % (Y _SIZE);627 size_t x = i / (YMAX); 628 size_t y = i % (YMAX); 640 629 641 630 #if USE_OPENMP … … 697 686 #endif 698 687 699 700 688 #if USE_PIC 689 701 690 ////////////////////////////////////////////////////////////////// 702 // IO bus and external peripherals in cluster[X_SIZE-1 ,Y_SIZE]691 // IO bus and external peripherals in cluster[X_SIZE-1][Y_SIZE-1] 703 692 // - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC 704 693 // - 3 local initiators : IOC, CMA, PIC … … 714 703 std::cout << std::endl; 715 704 716 size_t cluster_io = cluster(X _SIZE-1, Y_SIZE);705 size_t cluster_io = cluster(XMAX-1, YMAX); 717 706 718 707 //////////// vci_local_crossbar … … 752 741 maptabd, 753 742 NB_NIC_CHANNELS, 754 NIC_MAC4, 755 NIC_MAC2, 756 NIC_RX_NAME, 757 NIC_TX_NAME ); 743 0, // default MAC_4 address 744 0, // default MAC_2 address 745 1 ); // NIC_MODE_SYNTHESIS 758 746 759 747 ///////////// vci_chbuf_dma … … 764 752 IntTab(cluster_io, CDMA_SRCID), 765 753 IntTab(cluster_io, CDMA_TGTID), 766 64, // burst size754 64, // burst size 767 755 NB_CMA_CHANNELS ); 768 756 … … 795 783 VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>* 796 784 wt_iobus = new VciDspinTargetWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>( 797 "wt_ bdev",785 "wt_iobus", 798 786 vci_srcid_width ); 799 787 800 788 VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>* 801 789 wi_iobus = new VciDspinInitiatorWrapper<vci_param_int, dspin_cmd_width, dspin_rsp_width>( 802 "wi_ bdev",790 "wi_iobus", 803 791 vci_srcid_width ); 804 792 805 793 /////////////////////////////////////////////////////////////// 806 // Net-list794 // IObus Net-list 807 795 /////////////////////////////////////////////////////////////// 808 796 … … 887 875 // NB_NIC_CHANNELS <= 2 888 876 // NB_CMA_CHANNELS <= 4 889 // NB_TTY_CHANNELS <= 8877 // NB_TTY_CHANNELS <= 16 890 878 iopic->p_clk (signal_clk); 891 879 iopic->p_resetn (signal_resetn); … … 903 891 else if(i < 16) iopic->p_hwi[i] (signal_irq_false); 904 892 else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]); 905 else if(i < 24) iopic->p_hwi[i] (signal_irq_false);906 else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_false);907 // else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_tx[i-24]);908 893 else iopic->p_hwi[i] (signal_irq_false); 909 894 } … … 915 900 wi_iobus->p_resetn (signal_resetn); 916 901 wi_iobus->p_vci (signal_vci_cmd_to_noc); 917 wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X _SIZE-1][Y_SIZE-1][NORTH]);918 wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X _SIZE-1][Y_SIZE-1][NORTH]);902 wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH]); 903 wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH]); 919 904 920 905 // vci/dspin wrappers … … 922 907 wt_iobus->p_resetn (signal_resetn); 923 908 wt_iobus->p_vci (signal_vci_cmd_from_noc); 924 wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X _SIZE-1][Y_SIZE-1][NORTH]);925 wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X _SIZE-1][Y_SIZE-1][NORTH]);926 927 #endif // USE_PIC909 wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH]); 910 wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH]); 911 912 #endif // USE_PIC 928 913 929 914 // Clock & RESET for clusters 930 for (size_t x = 0; x < (X _SIZE); x++)931 { 932 for (size_t y = 0; y < (Y _SIZE); y++)915 for (size_t x = 0; x < (XMAX); x++) 916 { 917 for (size_t y = 0; y < (YMAX); y++) 933 918 { 934 919 clusters[x][y]->p_clk (signal_clk); … … 938 923 939 924 // Inter Clusters horizontal connections 940 if (X _SIZE> 1)941 { 942 for (size_t x = 0; x < (X _SIZE-1); x++)925 if (XMAX > 1) 926 { 927 for (size_t x = 0; x < (XMAX-1); x++) 943 928 { 944 for (size_t y = 0; y < (Y _SIZE); y++)929 for (size_t y = 0; y < (YMAX); y++) 945 930 { 946 931 clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]); … … 974 959 975 960 // Inter Clusters vertical connections 976 if (Y _SIZE> 1)977 { 978 for (size_t y = 0; y < (Y _SIZE-1); y++)961 if (YMAX > 1) 962 { 963 for (size_t y = 0; y < (YMAX-1); y++) 979 964 { 980 for (size_t x = 0; x < X _SIZE; x++)965 for (size_t x = 0; x < XMAX; x++) 981 966 { 982 967 clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]); … … 1010 995 1011 996 // East & West boundary cluster connections 1012 for (size_t y = 0; y < (Y _SIZE); y++)997 for (size_t y = 0; y < (YMAX); y++) 1013 998 { 1014 999 clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]); 1015 1000 clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]); 1016 clusters[X _SIZE-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]);1017 clusters[X _SIZE-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]);1001 clusters[XMAX-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[XMAX-1][y][EAST]); 1002 clusters[XMAX-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[XMAX-1][y][EAST]); 1018 1003 1019 1004 clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]); 1020 1005 clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]); 1021 clusters[X _SIZE-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]);1022 clusters[X _SIZE-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]);1006 clusters[XMAX-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[XMAX-1][y][EAST]); 1007 clusters[XMAX-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[XMAX-1][y][EAST]); 1023 1008 1024 1009 clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]); 1025 1010 clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]); 1026 clusters[X _SIZE-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]);1027 clusters[X _SIZE-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]);1011 clusters[XMAX-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[XMAX-1][y][EAST]); 1012 clusters[XMAX-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[XMAX-1][y][EAST]); 1028 1013 1029 1014 clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]); 1030 1015 clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]); 1031 clusters[X _SIZE-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]);1032 clusters[X _SIZE-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]);1016 clusters[XMAX-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[XMAX-1][y][EAST]); 1017 clusters[XMAX-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[XMAX-1][y][EAST]); 1033 1018 1034 1019 clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]); 1035 1020 clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]); 1036 clusters[X _SIZE-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]);1037 clusters[X _SIZE-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]);1021 clusters[XMAX-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[XMAX-1][y][EAST]); 1022 clusters[XMAX-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[XMAX-1][y][EAST]); 1038 1023 } 1039 1024 … … 1041 1026 1042 1027 // North & South boundary clusters connections 1043 for (size_t x = 0; x < X _SIZE; x++)1028 for (size_t x = 0; x < XMAX; x++) 1044 1029 { 1045 1030 clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]); 1046 1031 clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]); 1047 clusters[x][Y _SIZE-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]);1048 clusters[x][Y _SIZE-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]);1032 clusters[x][YMAX-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][YMAX-1][NORTH]); 1033 clusters[x][YMAX-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][YMAX-1][NORTH]); 1049 1034 1050 1035 clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]); 1051 1036 clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]); 1052 clusters[x][Y _SIZE-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]);1053 clusters[x][Y _SIZE-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]);1037 clusters[x][YMAX-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][YMAX-1][NORTH]); 1038 clusters[x][YMAX-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][YMAX-1][NORTH]); 1054 1039 1055 1040 clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]); 1056 1041 clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]); 1057 clusters[x][Y _SIZE-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]);1058 clusters[x][Y _SIZE-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]);1042 clusters[x][YMAX-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][YMAX-1][NORTH]); 1043 clusters[x][YMAX-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][YMAX-1][NORTH]); 1059 1044 1060 1045 clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]); 1061 1046 clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]); 1062 clusters[x][Y _SIZE-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]);1063 clusters[x][Y _SIZE-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]);1047 clusters[x][YMAX-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][YMAX-1][NORTH]); 1048 clusters[x][YMAX-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][YMAX-1][NORTH]); 1064 1049 1065 1050 clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]); 1066 1051 clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]); 1067 clusters[x][Y _SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]);1068 clusters[x][Y _SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]);1052 clusters[x][YMAX-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][YMAX-1][NORTH]); 1053 clusters[x][YMAX-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][YMAX-1][NORTH]); 1069 1054 } 1070 1055 … … 1083 1068 // set network boundaries signals default values 1084 1069 // for all boundary clusters but the IO cluster 1085 for (size_t x = 0; x < X _SIZE; x++)1086 { 1087 for (size_t y = 0; y < Y _SIZE; y++)1070 for (size_t x = 0; x < XMAX ; x++) 1071 { 1072 for (size_t y = 0; y < YMAX ; y++) 1088 1073 { 1089 1074 for (size_t face = 0; face < 4; face++) 1090 1075 { 1091 if ( (x != X _SIZE-1) or (y != Y_SIZE-1) or (face != NORTH) )1076 if ( (x != XMAX-1) or (y != YMAX-1) or (face != NORTH) ) 1092 1077 { 1093 1078 signal_dspin_bound_cmd_in [x][y][face].write = false; … … 1121 1106 1122 1107 #if USE_PIC == 0 1123 signal_dspin_bound_cmd_in[X _SIZE-1][Y_SIZE-1][NORTH].write = false;1124 signal_dspin_bound_rsp_out[X _SIZE-1][Y_SIZE-1][NORTH].read = true;1125 signal_dspin_bound_cmd_out[X _SIZE-1][Y_SIZE-1][NORTH].read = true;1126 signal_dspin_bound_rsp_in[X _SIZE-1][Y_SIZE-1][NORTH].write = false;1108 signal_dspin_bound_cmd_in[XMAX-1][YMAX-1][NORTH].write = false; 1109 signal_dspin_bound_rsp_out[XMAX-1][YMAX-1][NORTH].read = true; 1110 signal_dspin_bound_cmd_out[XMAX-1][YMAX-1][NORTH].read = true; 1111 signal_dspin_bound_rsp_in[XMAX-1][YMAX-1][NORTH].write = false; 1127 1112 #endif 1128 1113 … … 1141 1126 } 1142 1127 1143 #if USE_PIC 1144 // variable used for IRQ trace 1145 bool prev_irq_bdev = false; 1146 bool prev_irq_mtty_rx[8]; 1147 bool prev_irq_proc[16][16][4]; 1148 1149 for( size_t x = 0 ; x<8 ; x++ ) prev_irq_mtty_rx[x] = false; 1150 1151 for( size_t x = 0 ; x<16 ; x++ ) 1152 for( size_t y = 0 ; y<16 ; y++ ) 1153 for( size_t i = 0 ; i<4 ; i++ ) prev_irq_proc[x][y][i] = false; 1154 #endif 1155 1128 // simulation loop 1156 1129 for (uint64_t n = 1; n < ncycles && !stop_called; n++) 1157 1130 { 1158 // Monitor a specific address for L1 & L2 caches1131 // Monitor a specific address for L1 cache 1159 1132 // clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL); 1160 // clusters[1][1]->memc->cache_monitor(0x110002c078ULL); 1133 1134 // Monitor a specific address for L2 cache 1135 // clusters[1][1]->memc->cache_monitor(0x200000F000ULL); 1136 1137 // Monitor a specific address for one XRAM 1138 // clusters[0][0]->xram->start_monitor( 0x200000F00ULL , 64); 1161 1139 1162 1140 // stats display … … 1186 1164 { 1187 1165 std::cout << "****************** cycle " << std::dec << n ; 1188 std::cout << " ******************************************** ****" << std::endl;1166 std::cout << " ********************************************" << std::endl; 1189 1167 1190 1168 size_t l = 0; … … 1207 1185 clusters[x][y]->xicu->print_trace(0); 1208 1186 clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str()); 1187 1188 if ( clusters[x][y]->signal_proc_irq[0] ) 1189 std::cout << "### IRQ_PROC_" << x << "_" << y << "_0" << std::endl; 1190 if ( clusters[x][y]->signal_proc_irq[4] ) 1191 std::cout << "### IRQ_PROC_" << x << "_" << y << "_1" << std::endl; 1192 if ( clusters[x][y]->signal_proc_irq[8] ) 1193 std::cout << "### IRQ_PROC_" << x << "_" << y << "_2" << std::endl; 1194 if ( clusters[x][y]->signal_proc_irq[12] ) 1195 std::cout << "### IRQ_PROC_" << x << "_" << y << "_3" << std::endl; 1209 1196 } 1210 1197 … … 1257 1244 signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); 1258 1245 signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); 1246 1247 // trace external interrupts 1248 if (signal_irq_bdev) std::cout << "### IRQ_BDEV" << std::endl; 1259 1249 #else 1260 1250 clusters[0][0]->bdev->print_trace(); … … 1263 1253 #endif 1264 1254 1265 // trace internal tty1266 // clusters[0][0]->mtty->print_trace();1267 // clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY");1268 1269 1255 } // end trace 1270 1271 #if 01272 #if USE_PIC1273 // trace BDV interrupts events1274 if ( signal_irq_bdev.read() != prev_irq_bdev )1275 {1276 prev_irq_bdev = signal_irq_bdev.read();1277 std::cout << std::dec << "@@@ IRQ_BDEV = " << signal_irq_bdev.read()1278 << " at cycle " << n << std::endl;1279 }1280 1281 // trace TTY interrupts events1282 for ( size_t x = 0 ; x < 8 ; x++ )1283 {1284 if ( signal_irq_mtty_rx[x].read() != prev_irq_mtty_rx[x] )1285 {1286 prev_irq_mtty_rx[x] = signal_irq_mtty_rx[x].read();1287 std::cout << std::dec << "@@@ IRQ_MTTY["<<x<<"] = "1288 << signal_irq_mtty_rx[x].read()1289 << " at cycle " << n << std::endl;1290 }1291 }1292 // trace VCI transactions on IOPIC and XCU(0,0)1293 signal_vci_tgt_iopi.print_trace("@@@ IOPI_TGT");1294 signal_vci_ini_iopi.print_trace("@@@ IOPI_INI");1295 #endif1296 1297 // trace processor interrupts events1298 for ( size_t x = 0 ; x < X_SIZE ; x++ )1299 for ( size_t y = 0 ; y < Y_SIZE ; y++ )1300 for ( size_t i = 0 ; i < NB_PROCS_MAX ; i++ )1301 {1302 if ( clusters[x][y]->signal_proc_irq[i] != prev_irq_proc[x][y][i] )1303 {1304 prev_irq_proc[x][y][i] = clusters[x][y]->signal_proc_irq[i];1305 std::cout << std::dec << "@@@ IRQ_PROC["<<x<<","<<y<<","<<i<<"] = "1306 << clusters[x][y]->signal_proc_irq[i]1307 << " at cycle " << n << std::endl;1308 }1309 }1310 1311 clusters[0][0]->signal_vci_tgt_xicu.print_trace("@@@ XCU_0_0");1312 #endif1313 1256 1314 1257 sc_start(sc_core::sc_time(1, SC_NS));
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