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Diff Rev Age Author Log Message
(edit) @155   14 years alain ntroducing the tsarv4_generic_ring platform
(edit) @154   14 years alain Introducing the tsarv4_generic_xbar platform
(edit) @153   14 years alain one more bug fixed…
(edit) @152   14 years kane Re add vci_cc_xcache_wrapper_v4 "multi-cache" edition and (1) fix …
(edit) @151   14 years alain Introducing the vci_block_device_tsar_v4 component, that respect the …
(edit) @150   14 years alain bug fixing
(edit) @149   14 years alain bug fixing
(edit) @148   14 years alain Introducing two new components : vci_vdspin_initiator_wrapper & …
(edit) @147   14 years alain Return to version 134 : The multi-processor version of the L1 cache …
(edit) @146   14 years choichil Modifications to make the code easier to read
(edit) @145   14 years choichil Adding function to get Latencies and a period for broadcast calculated …
(edit) @144   14 years kane in vci_cc_xcache_wrapper_v4 : (1) Fix bug in MISS_VICTIM state, (2) …
(edit) @143   14 years kane fix bug in ccxcachev4, save cpu_info in memcachev4
(edit) @142   14 years guthmull Eviction can now be random. Unselected by default.
(edit) @141   14 years guthmull Improve activity counters. Table sizes are now instance parameters.
(edit) @140   14 years kane yAjout du multi_cache : plusieurs processeur peuvent ce partager le …
(edit) @139   14 years gao Cleanup FSM changed
(edit) @138   14 years guthmull Handle bad accesses cleanly : transmit all accesses to the xram and …
(edit) @137   14 years simerabe replacing old ring versions with new one
(edit) @136   14 years simerabe deleting old ring components
(edit) @135   14 years choichil Initiator with bug correction in latency computing
(edit) @134   14 years kane add multi write buffer in cc_xcache_v4
(edit) @133   14 years choichil Platform with more parameters
(edit) @132   14 years choichil Synthetic Initiator with the latests bugs fixed
(edit) @131   14 years choichil Initiator with only one FSM for responses
(edit) @130   14 years gao Cleanup fsm seperated from vci fsm to evite deadlock
(edit) @129   14 years alain
(edit) @128   14 years alain decreasing the number of registers
(edit) @127   14 years choichil Removing useless prints
(edit) @126   14 years choichil Synthetic Initiator only with sc_signal
(edit) @125   14 years choichil Synthetic Initiator with good data to print
(edit) @124   14 years choichil Synthetic Initiator…
(edit) @123   14 years choichil Synthetic Initiator with parallel transactions
(edit) @122   14 years choichil Synthetic Initiator before being change for multiple requests
(edit) @121   14 years choichil Generic platform for VDSPIN tests and measurements
(edit) @120   14 years gao Separated cleanup from the vci_fsm to avoid deadlock
(edit) @119   14 years gao Modification for synthetisable reason
(edit) @118   14 years alain update print_trace() prototype
(edit) @117   14 years alain Introducing two generic hardware platforms: - tsarv4_vgmn_generic_32 - …
(edit) @116   14 years alain Introducing a print_trace() method
(edit) @115   14 years choichil Adding deterministic for debug
(edit) @114   14 years alain Improving the print_trace() display.
(edit) @113   14 years alain Improving the print_trace() function
(edit) @112   14 years choichil Platform that works…
(edit) @111   14 years choichil Puisque c'est comme ça, je commite mon truc…
(edit) @110   14 years guthmull Fix an issue with systemcass 64 bits conversions.
(edit) @109   14 years guthmull Don't check rsp length in case of error. Check that the processor …
(edit) @108   14 years gao Bug correction
(edit) @107   14 years guthmull Add a simple TsarV4 platform
(edit) @106   14 years choichil Vci_Synthetic_Initiator correction of some bugs... some may still exist
(edit) @105   14 years choichil PF ended
(edit) @104   14 years gao Verify broadcast address using mask
(edit) @103   14 years choichil Platform using vci_simple_ram which is not the svn working copy (allow …
(edit) @102   14 years choichil Synthetic initiator that compiles
(edit) @101   14 years gao Delete the evaluation codes for speedup simulation
(edit) @100   14 years choichil Deleting modelsim files
(edit) @99   14 years choichil Platform without targets
(edit) @98   14 years choichil Correcting file names of vci_synthetic_initiator
(edit) @97   14 years choichil Draft of new platform with VciSyntheticInitiator? and VDSPIN
(edit) @96   14 years gao Redo ins TLB access bit update when it miss in dcache
(edit) @95   14 years choichil Platform with DMA and FB
(edit) @94   14 years choichil Deleting work directory
(edit) @93   14 years choichil Platform with DMA
(edit) @92   14 years choichil Platform with DMA VHDL
(edit) @91   14 years alain polishing
(edit) @90   14 years alain Introducing a print_trace() method for debug.
(edit) @89   14 years simerabe fixing bug vci_ring_initiator : fifo_wok
(edit) @88   14 years gao Correction of itlb access bit set and dtlb dirty bit set
(edit) @87   14 years simerabe platform for new vdspin_router/vci_local_ring_fast
(edit) @86   14 years simerabe simple_ring_fast platform
(edit) @85   14 years simerabe removing duplicate ring_signals_2
(edit) @84   14 years bouyer ICACHE_SW_FLUSH/ICACHE_CACHE_FLUSH: when walking the tlb/cache looking …
(edit) @83   14 years guthmull Fix the masking of RERROR field
(edit) @82   14 years guthmull Add broadcast limitation compatibility, indicate the type of response …
(edit) @81   14 years choichil vci_synthetic_initiator draft
(edit) @80   14 years gao Modified the coherence check for TLB entry updating
(edit) @79   14 years gao Correction of dirty bit and access bit in data cache
(edit) @78   14 years choichil Modification of the vci_synthetic_initiator draft
(edit) @77   14 years choichil Rename of vci_traffic_generator to vci_synthetic_initiator
(edit) @76   14 years choichil Metadata file…
(edit) @75   14 years choichil Rearranging hierarchy
(edit) @74   14 years choichil Adding files hierarchy of vci_traffic_generator
(edit) @73   14 years bouyer Fix several issues regarding management of the …
(edit) @72   14 years bouyer 2 fixes: - do not test r_dcache_in_[id]tlb[] just after setting the …
(edit) @71   14 years bouyer When updating PTE bits, don't write back to the dcache locally, the …
(edit) @70   14 years bouyer Check/update the dirty bit on SC too
(edit) @69   14 years bouyer Fix cut'n'paste error
(edit) @68   14 years bouyer A SC cause the dcache entry to be updated by the memcache, and the tlb …
(edit) @67   14 years nipo Namespaces
(edit) @66   14 years nipo Namespaces
(edit) @65   14 years nipo Use proper namespaces
(edit) @64   14 years nipo Use proper namespaces
(edit) @63   14 years nipo Use proper namespaces
(edit) @62   14 years gao Debug infos deleted
(edit) @61   14 years gao Active caches
(edit) @60   15 years gao bug correction
(edit) @59   15 years alain modifying the chek in the constructor to accept up to 4096 sets.
(edit) @58   15 years guthmull Fix partial instruction updates
(edit) @57   15 years guthmull Fix a bug with uncached reads, add more debug capabilities
(edit) @56   15 years guthmull SC don't generate invalidations and cleanup any more, add treatment of …
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