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Diff Rev Age Author Log Message
(edit) @342   12 years joannou Introducing tsar_generic_mmu_dspin_coherence platform (ring dspin for …
(edit) @341   12 years joannou In vci_cc_vcache_wrapper_dspin_coherence, DCACHE_TLB_PTE1_MISS and …
(edit) @340   12 years cfuguet Erasing always false condition in the if statement of the …
(edit) @339   12 years cfuguet Erasing always false condition in the if statement of the …
(edit) @338   12 years joannou * In vci_cc_vcache_wrapper_dspin_coherence, modified both states …
(edit) @337   12 years joannou In generic_cache_tsar, added new read function that returns 2 32bits …
(edit) @336   12 years cfuguet Bug fix in the vci_cc_vcache_wrapper and vci_mem_cache components (and …
(edit) @335   12 years joannou Added llsc table initialization in both vci_mem_cache and …
(edit) @334   12 years joannou Separated stat counters resets from internal registers resets
(edit) @333   12 years joannou - In vci_cc_vcache_wrapper_dspin_coherence : initializing …
(edit) @332   12 years joannou Updated top.cpp in tsar_mono_mmu_dspin_coherence to respect new file …
(edit) @331   12 years joannou Renaming all files form vci_cc_vcache_wrapper_dspin_coherence and …
(edit) @330   12 years joannou * Commented debug in dspin_local_ring_fast_c * Added test on plen …
(edit) @329   12 years joannou Added test on INST/DATA for the CLACK in the …
(edit) @328   12 years cfuguet Including TYPE_CLEANUP_ACK_INST and TYPE_CLEANUP_ACK_DATA in the …
(edit) @327   12 years simerabe introducing topcell examples using dspin ring interconnect
(edit) @326   12 years simerabe introducing 2 new components : simple and local ring interconnect …
(edit) @325   12 years joannou bugfix in vci_cc_vcache_wrapper_dspin_coherence : - consume fifo in …
(edit) @324   12 years joannou updated the test_interrupt_delayslot : now testing for several delay values
(edit) @323   12 years joannou removed unusefull flipflop r_*cache_cc_fifo_done + syntax correction …
(edit) @322   12 years cfuguet Erasing binary generated files in tests_ccvcache_v4/test_sync from the repo
(edit) @321   12 years joannou bugfix in vci_cc_vcache_wrapper_dspin_coherence in coherence type checking
(edit) @320   12 years cfuguet vci_mem_cache_dspin_coherence: - Fixing typo error in …
(edit) @319   12 years cfuguet Fix bug in vci_mem_cache_dspin_coherence. The write signal in the …
(edit) @318   12 years joannou vci_cc_vcache_wrapper_dspin_coherence now use DspinDhccpParam::* types …
(edit) @317   12 years cfuguet Introducing missing debug strings in the vci_mem_cache cpp file
(edit) @316   12 years joannou Introducing new tsar_mono_mmu_dspin_coherence platform Same as …
(edit) @315   12 years joannou Introducing new dspin interface for …
(edit) @314   12 years cfuguet Erasing old comments in the reset.s file of the pre-loader
(edit) @313   12 years cfuguet Erasing useless template parameters for the …
(edit) @312   12 years cfuguet Updating width of the way index in DSPIN coherence flits. Using 2 bits …
(edit) @311   12 years cfuguet Including GET and SET methods for the FROM_L1_BC and FROM_MC_BC bit in …
(edit) @310   12 years cfuguet Introducing FROM_L1_BC and FROM_MC_BC in dspin param class to access …
(edit) @309   12 years joannou Bugfix : typo in component name (was 'dhcpp', is now 'dhccp')
(edit) @308   12 years cfuguet Fixing parameter name error in metadata of vci_mem_cache
(edit) @307   12 years cfuguet Including vci_mem_cache v5 using dspin interface for the coherence …
(edit) @306   12 years joannou Added tsar_mono_mmu and tsar_generic_mmu platforms
(edit) @305   12 years joannou In vci_mem_cache component: Adding an assert for cleanup commands …
(edit) @304   12 years joannou Bug fixing in vci_cc_vcache_wrapper component : - In TGT_RSP_DCACHE, …
(edit) @303   12 years joannou Bug fix in generic_cache_tsar component : In the read_select function, …
(edit) @302   12 years cfuguet Introducing IRQ_PER_PROC constant in the tsar boot loader …
(edit) @301   12 years joannou bugfix in vci_block_device_tsar_v4 : the component used a vci …
(edit) @300   12 years joannou Moved tsar modules vci_cc_vcache_wrapper and vci_mem_cache under the …
(edit) @299   12 years alain bug fixing: coherence interrupt must be taken in the MISS_DIR_UPDT states.
(edit) @298   12 years alain Bug fixing in the NIC constructor
(edit) @297   12 years alain Introducing the 3 states (EMPTY,VALID,ZOMBI) states in cache directory
(edit) @296   12 years alain introducing major modifications in vci_cc_vcache_wrappers - remove …
(edit) @295   12 years cfuguet Introducing branches/v5/ components directory. This branch will be …
(edit) @294   12 years cfuguet Creating branch repertory for the TSAR svn repository. Copying the …
(edit) @293   12 years cfuguet Including Makefile for tsar boot loader
(edit) @292   12 years cfuguet Changing directory structure of the TSAR boot loader. A README.txt …
(edit) @291   12 years joannou Introducing new generic_llsc_local_table and generic_llsc_global_table …
(edit) @290   12 years cfuguet Erasing in the vci_mem_cache_v4 CLEANUP FSM the transition between the …
(edit) @289   12 years cfuguet Introducing cache data ram with bit masking in the Memory Cache. The …
(edit) @288   12 years joannou Bug fix in vci_cc_vcache_wrapper_v4 : unwanted reset of the …
(edit) @287   12 years joannou Updated vci_vdspin_initiator_wrapper and vci_vdspin_target_wrapper to …
(edit) @286   12 years cfuguet Fixing bug in boot_tty.c: Use address of tty status when reading with …
(edit) @285   12 years alain Fixing a bug identified by Hao: there was a dead-lock condition if: - …
(edit) @284   12 years joannou Updated of the vci trdid/rtrdid and pktid/rpktid fields for the direct …
(edit) @283   12 years joannou Changed default value to 0 for the L1_MULTI_CACHE define Fixed some …
(edit) @282   12 years bouyer Complete r281: Keep BEV bit set in STATUS register, and add an …
(edit) @281   12 years bouyer Keep BEV bit set in STATUS register, and add an exception handler at …
(edit) @280   12 years bouyer Remove unused base_addresses
(edit) @279   12 years cfuguet Introducing multi block read in the ioc_read function for the FPGA platform
(edit) @278   12 years bouyer The ring is cpu-ungry, so give one thread per ring when running under …
(edit) @277   12 years cfuguet Fixing bug in the alloc dir FSM. The READ FSM release the lock on the …
(edit) @276   12 years bouyer A boot loader to be stored in ROM of a TSAR platform. Based on Cesar …
(edit) @275   12 years bouyer This VHDL implementation uses rings, use rings here too.
(edit) @274   12 years bouyer Add a platform describing as closely as possible the hardware that is …
(edit) @273   12 years cfuguet Modificating the VCI Memory Cache to align the VHDL and the SOCLIB …
(edit) @272   12 years bouyer Fix writes: - properly compute r_buf_address, + has highter priority …
(edit) @271   12 years bouyer Remove useless file.
(edit) @270   12 years haoliu fix bug for test_sync
(edit) @269   12 years haoliu fix bug for test_sync
(edit) @268   12 years bouyer Dummy commit to test post-commit hook
(edit) @267   12 years bouyer Forced commit to test post-commit-hook
(edit) @266   12 years bouyer Sync with reality
(edit) @265   12 years bouyer Update/add 2 new tests, from tests_mips32_vcache: test_llsc: check …
(edit) @264   12 years bouyer We have big servers, so use some parallelism here
(edit) @263   12 years alain Introducing a network controller (vci_multi_nic) in the I0 cluster.
(edit) @262   12 years alain Bug fixing: The handling of L/R bit update has been modified in DCACHE …
(edit) @261   12 years alain The tsarv4_generic_mmu platform has been modified to use the …
(edit) @260   12 years alain The vci_block_device_tsar_v4 component has been modified to support …
(edit) @259   12 years almaless Introduce ALMOS used platforms for TSAR. See the package's README …
(edit) @258   12 years almaless Introduce a vci profiler for TSAR direct network
(edit) @257   12 years almaless - Adding two arguments: BLKSZ (sector size) and THREADS (OpenMP …
(edit) @256   12 years almaless Increase the set of allowed sector sizes until small-page size
(edit) @255   12 years alain Two modifications in the "tsarv4_generic_mmu" platform: 1) improving …
(edit) @254   12 years alain Two modifications: 1/ fixing a bug in the DCACHE_CC_INVAL state, …
(edit) @253   12 years meunier Added the display of the name of the component in the vci_cc_vcache_v4 …
(edit) @252   12 years meunier Minor changes on the soft_filter. This version works on tsar …
(edit) @251   12 years cfuguet Add the r_tgt_dcache_rsp and r_tgt_icache_rsp in the condition to go …
(edit) @250   12 years alain Removing parasitic constructor message.
(edit) @249   12 years meunier Formatting of topcell and cluster files
(edit) @248   12 years meunier Updates in the soft_filter application (bug corrections, formatting, …
(edit) @247   12 years cfuguet Introducing new CLEANUP transaction address specification in the …
(edit) @246   12 years cfuguet Bug fix in IXR_RSP FSM. Erroneous condition for the error verification
(edit) @245   12 years alain ntroducing a segmentation violation checking
(edit) @244   12 years meunier soft_transpose update to match platform changes
(edit) @243   12 years fraga Adding platform using vci_io_bridge
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