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Diff Rev Age Author Log Message
(edit) @359   13 years joannou bugfix : correctly updating the r_preempt register
(edit) @358   13 years simerabe bugfix : preempt in case of broadcast, palloc in case of single flit
(edit) @357   13 years simerabe fixbug : test on eop in case of single_flit coherence request
(edit) @356   13 years cfuguet Modifying comments in the dspin_dhccp_param to comply the type …
(edit) @355   13 years joannou In vci_cc_vcache_wrapper v5 - added check for p_dspin_in.write in …
(edit) @354   13 years cfuguet Bugfix in branches/v5/vci_mem_cache Adding missing condition in …
(edit) @353   13 years cfuguet Bugfix in branches/v5/vci_mem_cache Adding missing fifo get in case of …
(edit) @352   13 years cfuguet Bugfix in vci_cc_vcache_wrapper_v4: In case of SC or CAS command, the …
(edit) @351   13 years joannou Got rid of intermediate v5 version. _dspin_coherence versions changed …
(edit) @350   13 years alain Introducing Platform tsarv5_dspin_array, that can be used for TSAR …
(edit) @349   13 years cfuguet Rearranging addresses in the function pointer table to keep backward …
(edit) @348   13 years cfuguet Adding the boot_putc and the boot_getc in the functions pointer table …
(edit) @347   13 years cfuguet Introducing dcache line invalidation mechanism in the boot_ioc_read …
(edit) @346   13 years alain New contructors for vci_mem_cache & vci_cc_vcache, as we don't need …
(edit) @345   13 years alain Introducing the cluster component in tsarv5_generic_mmu platform.
(edit) @344   13 years alain Introducing the tsarv5_generic_mmu platform.
(edit) @343   13 years cfuguet Using the Xicu SOFT IRQs (IPIs). Adding them on the Xicu constructor
(edit) @342   13 years joannou Introducing tsar_generic_mmu_dspin_coherence platform (ring dspin for …
(edit) @341   13 years joannou In vci_cc_vcache_wrapper_dspin_coherence, DCACHE_TLB_PTE1_MISS and …
(edit) @340   13 years cfuguet Erasing always false condition in the if statement of the …
(edit) @339   13 years cfuguet Erasing always false condition in the if statement of the …
(edit) @338   13 years joannou * In vci_cc_vcache_wrapper_dspin_coherence, modified both states …
(edit) @337   13 years joannou In generic_cache_tsar, added new read function that returns 2 32bits …
(edit) @336   13 years cfuguet Bug fix in the vci_cc_vcache_wrapper and vci_mem_cache components (and …
(edit) @335   13 years joannou Added llsc table initialization in both vci_mem_cache and …
(edit) @334   13 years joannou Separated stat counters resets from internal registers resets
(edit) @333   13 years joannou - In vci_cc_vcache_wrapper_dspin_coherence : initializing …
(edit) @332   13 years joannou Updated top.cpp in tsar_mono_mmu_dspin_coherence to respect new file …
(edit) @331   13 years joannou Renaming all files form vci_cc_vcache_wrapper_dspin_coherence and …
(edit) @330   13 years joannou * Commented debug in dspin_local_ring_fast_c * Added test on plen …
(edit) @329   13 years joannou Added test on INST/DATA for the CLACK in the …
(edit) @328   13 years cfuguet Including TYPE_CLEANUP_ACK_INST and TYPE_CLEANUP_ACK_DATA in the …
(edit) @327   13 years simerabe introducing topcell examples using dspin ring interconnect
(edit) @326   13 years simerabe introducing 2 new components : simple and local ring interconnect …
(edit) @325   13 years joannou bugfix in vci_cc_vcache_wrapper_dspin_coherence : - consume fifo in …
(edit) @324   13 years joannou updated the test_interrupt_delayslot : now testing for several delay values
(edit) @323   13 years joannou removed unusefull flipflop r_*cache_cc_fifo_done + syntax correction …
(edit) @322   13 years cfuguet Erasing binary generated files in tests_ccvcache_v4/test_sync from the repo
(edit) @321   13 years joannou bugfix in vci_cc_vcache_wrapper_dspin_coherence in coherence type checking
(edit) @320   13 years cfuguet vci_mem_cache_dspin_coherence: - Fixing typo error in …
(edit) @319   13 years cfuguet Fix bug in vci_mem_cache_dspin_coherence. The write signal in the …
(edit) @318   13 years joannou vci_cc_vcache_wrapper_dspin_coherence now use DspinDhccpParam::* types …
(edit) @317   13 years cfuguet Introducing missing debug strings in the vci_mem_cache cpp file
(edit) @316   13 years joannou Introducing new tsar_mono_mmu_dspin_coherence platform Same as …
(edit) @315   13 years joannou Introducing new dspin interface for …
(edit) @314   13 years cfuguet Erasing old comments in the reset.s file of the pre-loader
(edit) @313   13 years cfuguet Erasing useless template parameters for the …
(edit) @312   13 years cfuguet Updating width of the way index in DSPIN coherence flits. Using 2 bits …
(edit) @311   13 years cfuguet Including GET and SET methods for the FROM_L1_BC and FROM_MC_BC bit in …
(edit) @310   13 years cfuguet Introducing FROM_L1_BC and FROM_MC_BC in dspin param class to access …
(edit) @309   13 years joannou Bugfix : typo in component name (was 'dhcpp', is now 'dhccp')
(edit) @308   13 years cfuguet Fixing parameter name error in metadata of vci_mem_cache
(edit) @307   13 years cfuguet Including vci_mem_cache v5 using dspin interface for the coherence …
(edit) @306   13 years joannou Added tsar_mono_mmu and tsar_generic_mmu platforms
(edit) @305   13 years joannou In vci_mem_cache component: Adding an assert for cleanup commands …
(edit) @304   13 years joannou Bug fixing in vci_cc_vcache_wrapper component : - In TGT_RSP_DCACHE, …
(edit) @303   13 years joannou Bug fix in generic_cache_tsar component : In the read_select function, …
(edit) @302   13 years cfuguet Introducing IRQ_PER_PROC constant in the tsar boot loader …
(edit) @301   13 years joannou bugfix in vci_block_device_tsar_v4 : the component used a vci …
(edit) @300   13 years joannou Moved tsar modules vci_cc_vcache_wrapper and vci_mem_cache under the …
(edit) @299   13 years alain bug fixing: coherence interrupt must be taken in the MISS_DIR_UPDT states.
(edit) @298   13 years alain Bug fixing in the NIC constructor
(edit) @297   13 years alain Introducing the 3 states (EMPTY,VALID,ZOMBI) states in cache directory
(edit) @296   13 years alain introducing major modifications in vci_cc_vcache_wrappers - remove …
(edit) @295   13 years cfuguet Introducing branches/v5/ components directory. This branch will be …
(edit) @294   13 years cfuguet Creating branch repertory for the TSAR svn repository. Copying the …
(edit) @293   13 years cfuguet Including Makefile for tsar boot loader
(edit) @292   13 years cfuguet Changing directory structure of the TSAR boot loader. A README.txt …
(edit) @291   13 years joannou Introducing new generic_llsc_local_table and generic_llsc_global_table …
(edit) @290   13 years cfuguet Erasing in the vci_mem_cache_v4 CLEANUP FSM the transition between the …
(edit) @289   13 years cfuguet Introducing cache data ram with bit masking in the Memory Cache. The …
(edit) @288   13 years joannou Bug fix in vci_cc_vcache_wrapper_v4 : unwanted reset of the …
(edit) @287   13 years joannou Updated vci_vdspin_initiator_wrapper and vci_vdspin_target_wrapper to …
(edit) @286   13 years cfuguet Fixing bug in boot_tty.c: Use address of tty status when reading with …
(edit) @285   13 years alain Fixing a bug identified by Hao: there was a dead-lock condition if: - …
(edit) @284   13 years joannou Updated of the vci trdid/rtrdid and pktid/rpktid fields for the direct …
(edit) @283   13 years joannou Changed default value to 0 for the L1_MULTI_CACHE define Fixed some …
(edit) @282   13 years bouyer Complete r281: Keep BEV bit set in STATUS register, and add an …
(edit) @281   13 years bouyer Keep BEV bit set in STATUS register, and add an exception handler at …
(edit) @280   13 years bouyer Remove unused base_addresses
(edit) @279   13 years cfuguet Introducing multi block read in the ioc_read function for the FPGA platform
(edit) @278   13 years bouyer The ring is cpu-ungry, so give one thread per ring when running under …
(edit) @277   13 years cfuguet Fixing bug in the alloc dir FSM. The READ FSM release the lock on the …
(edit) @276   13 years bouyer A boot loader to be stored in ROM of a TSAR platform. Based on Cesar …
(edit) @275   13 years bouyer This VHDL implementation uses rings, use rings here too.
(edit) @274   13 years bouyer Add a platform describing as closely as possible the hardware that is …
(edit) @273   13 years cfuguet Modificating the VCI Memory Cache to align the VHDL and the SOCLIB …
(edit) @272   13 years bouyer Fix writes: - properly compute r_buf_address, + has highter priority …
(edit) @271   13 years bouyer Remove useless file.
(edit) @270   13 years haoliu fix bug for test_sync
(edit) @269   13 years haoliu fix bug for test_sync
(edit) @268   13 years bouyer Dummy commit to test post-commit hook
(edit) @267   13 years bouyer Forced commit to test post-commit-hook
(edit) @266   13 years bouyer Sync with reality
(edit) @265   13 years bouyer Update/add 2 new tests, from tests_mips32_vcache: test_llsc: check …
(edit) @264   13 years bouyer We have big servers, so use some parallelism here
(edit) @263   13 years alain Introducing a network controller (vci_multi_nic) in the I0 cluster.
(edit) @262   13 years alain Bug fixing: The handling of L/R bit update has been modified in DCACHE …
(edit) @261   13 years alain The tsarv4_generic_mmu platform has been modified to use the …
(edit) @260   13 years alain The vci_block_device_tsar_v4 component has been modified to support …
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