[11] | 1 | # vis release 1.1 (compiled 25-Apr-96 at 11:35 AM) |
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| 2 | # network name: COHERANCE |
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| 3 | # generated: Tue May 14 18:26:43 1996 |
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| 4 | # |
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| 5 | # name type mddId vals levs |
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| 6 | proc1.proc_state latch 1 3 (0, 1) |
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| 7 | proc1.proc_state$NS shadow 2 3 (2, 3) |
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| 8 | inst1 primary-input 0 3 (4, 5) |
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| 9 | cc1.cache_state latch 3 5 (6, 7, 8) |
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| 10 | cc1.cache_state$NS shadow 4 5 (9, 10, 11) |
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| 11 | cache_req1 latch 10 4 (12, 13) |
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| 12 | cache_req1$NS shadow 11 4 (14, 15) |
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| 13 | cc1.block_state latch 31 3 (20, 21) |
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| 14 | cc1.block_state$NS shadow 32 3 (22, 23) |
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| 15 | direc.arbiter_state latch 46 6 (24, 25, 26) |
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| 16 | direc.arbiter_state$NS shadow 47 6 (27, 28, 29) |
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| 17 | any_address1<0> primary-input 7 2 (30) |
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| 18 | blk_add1<0> latch 8 2 (31) |
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| 19 | blk_add1<0>$NS shadow 9 2 (32) |
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| 20 | direc.cache_Wlist1<*1*> latch 20 2 (33) |
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| 21 | direc.cache_Wlist1<*1*>$NS shadow 21 2 (34) |
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| 22 | cc1.block_add<0> latch 5 2 (35) |
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| 23 | cc1.block_add<0>$NS shadow 6 2 (36) |
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| 24 | direc.cache_Wlist1<*0*> latch 22 2 (37) |
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| 25 | direc.cache_Wlist1<*0*>$NS shadow 23 2 (38) |
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| 26 | direc.cache_Rlist1<*1*> latch 24 2 (39) |
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| 27 | direc.cache_Rlist1<*1*>$NS shadow 25 2 (40) |
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| 28 | direc.cache_Rlist1<*0*> latch 26 2 (41) |
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| 29 | direc.cache_Rlist1<*0*>$NS shadow 27 2 (42) |
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| 30 | direc.cache_Rlist2<*0*> latch 16 2 (43) |
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| 31 | direc.cache_Rlist2<*0*>$NS shadow 17 2 (44) |
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| 32 | cc1.block_val latch 28 2 (45) |
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| 33 | cc1.block_val$NS shadow 29 2 (46) |
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| 34 | any_value1 primary-input 30 2 (47) |
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| 35 | direc.main_mem<*0*> latch 42 2 (48) |
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| 36 | direc.main_mem<*0*>$NS shadow 43 2 (49) |
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| 37 | direc.main_mem<*1*> latch 40 2 (50) |
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| 38 | direc.main_mem<*1*>$NS shadow 41 2 (51) |
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| 39 | cc2.block_val latch 37 2 (52) |
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| 40 | cc2.block_val$NS shadow 38 2 (53) |
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| 41 | any_value2 primary-input 39 2 (54) |
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| 42 | cc2.block_add<0> latch 53 2 (55) |
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| 43 | cc2.block_add<0>$NS shadow 54 2 (56) |
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| 44 | direc.cache_Rlist2<*1*> latch 18 2 (57) |
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| 45 | direc.cache_Rlist2<*1*>$NS shadow 19 2 (58) |
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| 46 | any_address2<0> primary-input 55 2 (59) |
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| 47 | cc2.block_state latch 44 3 (60, 61) |
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| 48 | cc2.block_state$NS shadow 45 3 (62, 63) |
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| 49 | direc.cache_Wlist2<*0*> latch 14 2 (64) |
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| 50 | direc.cache_Wlist2<*0*>$NS shadow 15 2 (65) |
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| 51 | direc.cache_Wlist2<*1*> latch 12 2 (66) |
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| 52 | direc.cache_Wlist2<*1*>$NS shadow 13 2 (67) |
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| 53 | blk_add2<0> latch 33 2 (68) |
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| 54 | blk_add2<0>$NS shadow 34 2 (69) |
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| 55 | proc2.proc_state latch 49 3 (70, 71) |
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| 56 | proc2.proc_state$NS shadow 50 3 (72, 73) |
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| 57 | inst2 primary-input 48 3 (74, 75) |
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| 58 | cc2.cache_state latch 51 5 (80, 81, 82) |
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| 59 | cc2.cache_state$NS shadow 52 5 (83, 84, 85) |
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| 60 | cache_req2 latch 35 4 (86, 87) |
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| 61 | cache_req2$NS shadow 36 4 (88, 89) |
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