source: vis_dev/vis-2.3/models/debug/and2.v @ 93

Last change on this file since 93 was 45, checked in by cecile, 13 years ago

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Line 
1module andgate(clk,a,b);
2input clk;
3input [1:0]a;
4input [1:0]b;
5
6reg [1:0]c;
7reg [1:0]d;
8
9initial c = 0;
10initial d = 0;
11
12
13always @(posedge clk)
14begin
15        c = a | b ;
16        d = a & b ;
17end
18endmodule 
19
20
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