source:
vis_dev/vis-2.3/models/debug/and2.v
@
106
Last change on this file since 106 was 45, checked in by , 13 years ago | |
---|---|
File size: 193 bytes |
Line | |
---|---|
1 | module andgate(clk,a,b); |
2 | input clk; |
3 | input [1:0]a; |
4 | input [1:0]b; |
5 | |
6 | reg [1:0]c; |
7 | reg [1:0]d; |
8 | |
9 | initial c = 0; |
10 | initial d = 0; |
11 | |
12 | |
13 | always @(posedge clk) |
14 | begin |
15 | c = a | b ; |
16 | d = a & b ; |
17 | end |
18 | endmodule |
19 | |
20 |
Note: See TracBrowser
for help on using the repository browser.