Changeset 36 for vis_dev/vis-2.3/models/debug/and2.v
- Timestamp:
- Jan 4, 2012, 12:03:00 PM (13 years ago)
- File:
-
- 1 edited
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vis_dev/vis-2.3/models/debug/and2.v
r33 r36 5 5 6 6 reg c; 7 wire x;8 wire y;9 7 10 8 initial c = 0; 11 9 12 assign x = a & b;13 assign y = (a)?b:x;14 10 15 11 always @(posedge clk) 16 12 begin 17 c = ~x + c;13 c = a & b ; 18 14 end 19 15 endmodule
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