Changeset 45 for vis_dev/vis-2.3/models
- Timestamp:
- Feb 20, 2012, 6:45:17 PM (13 years ago)
- File:
-
- 1 edited
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vis_dev/vis-2.3/models/debug/and2.v
r43 r45 1 1 module andgate(clk,a,b); 2 2 input clk; 3 input a;4 input b;3 input [1:0]a; 4 input [1:0]b; 5 5 6 reg c;7 reg d;6 reg [1:0]c; 7 reg [1:0]d; 8 8 9 9 initial c = 0;
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