Open position:

I have created the Analog IC&Tools group within the CIAN Team in the SoC department of LIP6 laboratory previously known as CAIRO, and now integrated in the FOS EDA Coriolis project. This project is meant to be the cornerstone of the Free and Open Source Hardware (FOSHW) concept.

The CIAN Team has regular cooperation with Professor Naohiko Shimizu, from Tokai University, Japan, on the Coriolis project. His CV may be downloaded here .

In LIP6, I am a member of 2 research axes:

  • Architecture, Systems and Network (ASN)
  • Safety, Security, and Reliability (SSR)

Since 2010, I am a member of the AMS Working Group of Accellera Systems Initiative and a contributer to the standardization the AMS extensions of SystemC. In January 2020, the SystemC Analog/Mixed-signal (AMS) Working Group has released its user guide for those who would like to use SystemC AMS extensions for their system-level design and verification work. It is meant as an introductory guide for electronic system-level engineers and architects; it explains the modeling fundamentals and gives examples on how to start with AMS system-level design at higher levels of abstraction. For more information on SystemC AMS and to download the new user guide, visit the SystemC AMS Working Group page.

I am currently the Scientific contact for Sorbonne Université and CNRS in the Go IT! European project (2022-2025).

  • Horizon-CL4-2021-Digital-Emerging/Coordination and Support Action/Go IT!: Europe's IT hardware development is constantly challenged by outrageously expensive development tools, legal constraints like NDAs or patents, lock-in threats, dependency from external vendors or supply chains and foreign political events. Europe’s digital infrastructure (from consumer to critical appliances) is heavily relying on foreign closed-source chips which are literally black-boxes which may (and have been proven to) contain malicious features. This situation makes the hardware development expensive and inefficient, and undermines the very principle of sovereignty, resilience and re-usability. Open-source silicon chips, which are open in their entirety, i.e. down to the physical layout, carry the potential of catapulting Europe into a renaissance of digital technology. Several challenges are on the way, many of which will require the participation of the stakeholders (from the fertile ground made of “nerdy” hobbyists and makers who are the early protagonists of the scene, all the way up to large enterprises), as well as the participation of policymakers and regulatory bodies. The road ahead is steep, but rich of rewards. Therefore we loudly say: Go IT!

I have contributed to several European research projects :

  • Eureka/PENTA/HADES: Hierarchy-Aware and secure embedded test infrastructure for Dependability and performance Enhancement of integrated Systems (2017-2021)
  • Echopen: Designing an Open Source and Low-Cost Echo-Stethoscope (2018-2021)
  • Catrene/H-Inception: Heterogeneous System Virtual Prototyping (2012-2015)
  • FP7/AUTOMICS: Pragmatic Solution for parasitic-immune design of electronics ICs for automotive (2012-2015)
  • FP7/VERDI: Verification for Heterogeneous Reliable Design and Integration (2011-2014)
  • Medea+/Beyond Dreams: Design refinement of Embedded Analog and Mixed-Signal System (2008-2011)
  • NANO2012: Design of AMS IPs, specially : Sigma Delta A/D Converters (2009-2012)

As well as National projects :

  • RAPID FLEXyRADIO: FLot de conception Et composants innovants dédiés à l’IoT et auX systèmes RADIOcom (2017-2022)
  • ANR/EDITSoC: Diagnostic Electrique des Systèmes-sur-Puce dédiés aux Applications IoT pour le Secteur Automobile (2018-2021)
  • ANR/WASABI: Wireless systems And SystemC-AMS Basic Infrastructure (2008-2011)