Virtual library

Description

The virtual library permits to create a cell and map it to different libraries without having to change it.

List of the generators provided

• a2 : q <= i0 & i1
• a3 : q <= i0 & i1 & i2
• a4 : q <= i0 & i1 & i2 & i3
• na2 : nq <= ~ ( i0 & i1 )
• na3 : nq <= ~ ( i0 & i1 & i2 )
• na4 : nq <= ~ ( i0 & i1 & i2 & i3 )
• o2 : q <= i0 & i1
• o3 : q <= i0 & i1 & i2
• o4 : q <= i0 & i1 & i2 & i3
• no2 : nq <= ~ ( i0 & i1 )
• no3 : nq <= ~ ( i0 & i1 & i2 )
• no4 : nq <= ~ ( i0 & i1 & i2 & i3 )
• inv : nq <= ~ i
• buf : q <= i
• xr2 : q <= i0 ^ i1
• nxr2 : nq <= ~ ( i0 ^ i1 )
• zero : nq <= '0'
• one : q <= '1'
• halfadder : sout <= a ^ b and cout <= a & b
• fulladder : sout <= a ^ b ^ cin
  and cout <= ( a & b ) | ( a & cin ) | ( b & cin )
• mx2 : q <= (i0 & ~cmd) | (i1 & cmd)
• nmx2 : nq <= ~( (i0 & ~cmd) | (i1 & cmd) )
• sff : if RISE ( ck ) : q <= i
• sff2 : if RISE ( ck ) : q <= (i0 & ~cmd) | (i1 & cmd)
• sff3 : if RISE ( ck ) :
q <= (i0 & ~cmd0) | (((i1 & cmd1)|(i2&~cmd1)) & cmd0)
• ts : if cmd : q <= i
• nts : if cmd : nq <= ~i

Mapping file

The virtual library is mapped to the sxlib library. A piece of the corresponding mapping file is shown below.
In order to map the virtual library to another library, on has to write a .xml file which makes correspond models and interfaces.
Note that the interfaces of the cells must be the same (except for the names of the ports). Otherwise, one has to create .vst file in order to make the interfaces match.

The environment variable used to point the right file is STRATUS_MAPPING_NAME.

Generators

Some generators are also provided in order to use the cells of the library with nets of more than 1 bit. One has to upper the first letter of the model name in order to user those generators. What is simply done is a for loop with the bits of the nets. The parameter 'nbit' gives the size of the generator.

Example

• Direct instanciation of a cell

for i in range ( 4 ) :
  Inst ( 'a2'
       , map = { 'i0'  : neti0[i]
               , 'i1'  : neti1[i]
               , 'q'   : netq[i]
               , 'vdd' : netvdd
               , 'vss' : netvss
               }
       )

• Instanciation of a generator

Generate ( 'A2', "my_and2_4bits", param = { 'nbit' : 4 } )
Inst ( 'my_and2_4bits'
     , map  = { 'i0'  : neti0
              , 'i1'  : neti1
              , 'q'   : netq
              , 'vdd' : vdd
              , 'vss' : vss
              }
     )

Errors

Some errors may occur :

• [Stratus ERROR] Inst : the model ... does not exist.
Check CRL_CATA_LIB.
  The model of the cell has not been found. One has to check the environment variable.
• [Stratus ERROR] Virtual library : No file found in order to parse.
Check STRATUS_MAPPING_NAME.
  The mapping file is not given in the environment variable.

See Also

Introduction