Projets de l'Équipe CIAN


eu logo GoIT logo Participants M.-M. Louerat, R. Chotin-Avot J.-P. Chaput
Durée 2022-2025
Partenaires EDI (Coordinator), CSIC, FSI(I), FibraServi, G-INP
Web Site GoIT Project

Open-source silicon chips, which are open in their entirety, i.e. down to the physical layout, carry the potential of catapulting Europe into a renaissance of digital technology. Several challenges are on the way, many of which will require the participation of the stakeholders (from the fertile ground made of “nerdy” hobbyists and makers who are the early protagonists of the scene, universities and research institutes who have the talent and power to teach students how to design Open-source Integrated Circuit (Intellectual Masterwork, IMW), all the way up to large enterprises), as well as the participation of policymakers and regulatory bodies. The road ahead is steep, but rich of rewards. Therefore we loudly say: GoIT!

LIP6 (SU-CNRS) hosts the organization of the FSiC conference, since the first editions. LIP6 (SU-CNRS) is mainly involved in the workpackage 3, "Hub of Open-Source EDA software" Coriolis and workpackage 5, Open-Source standard Cell Library within GoIT project.

The GoIT consortium is in charge of the FSiC 2023, FSiC 2024, FSiC 2025 conference organization. The goal of FSiC is to make the technology accessible to small businesses, startups, universities and schools. Students, makers and professional should have direct access to education, without barriers, paywalls and legal burdens. What's the value of multi-billion public investments if there aren't designers, engineers and other experts who can operate the industry and who master the tools to innovate? We all took apart watches and radios when we were kids, hence we learned how they work. It is time to look inside chips and their tool-chains so that we can study, improve, repair and trust them.

FSiC motto is therefore: Education, sustainability and innovation by openness and collaboration!

Wasga Server

Logo BPI France Logo Pole Systematic Participants H. Mehrez, R. Chotin-Avot
Durée 2014-2018
Partenaires Bull, CEA, Refex
Conception d'un accélérateur matériel hybride à base de FPGA

Heterogeneous Inception

Logo Catrene Logo MEDEA+ Logo DGE Logo H-Inception Participants M.-M. Louerat, H. Aboushady, F. Pecheux
Durée 2012-2015
Partenaires AlphaSip, Atrenta, Coventor, Continental, Dizain-Sync, Fraunhofer Institute, ST Microelectronics, Magillem Design Service, Oce, Reden, SmartSigns, IMEC, EPFL, INL, TU Delft, University Cantabria, University Zaragosa
Web Site Projet H-Inception
The general goal of H-INCEPTION is to develop and deploy a unified design environment for virtual prototyping of multi-domain microelectronics assisted systems to overcome the challenges related to their specification, dimensioning and verification


Logo Catrene Logo MEDEA+ Participants M.-M. Louerat, H. Aboushady, F. Pecheux
Durée 2008-2011
Partenaires Infineon, BOSCH, Fraunhofer Institute, ST Microelectronics, Magillem Design Service, TUV, CEA-LETI, TIMA, NXP, Dizain-Sync, TIWMC, TU Delft, IMEC-NL, EPFL
Design refinement of embedded analog and mixed-signal systems


UE Flag Logo FP7 UE Flag Participants R. Iskander, M.-M. Louerat, J.-P. Chaput
Durée 2012-2015
Partenaires AdMOS, AMS AG, Continental, ST Microelectronics, Valeo, EPFL, LAAS
Web Site
Pragmatic solution for parasitic-immune design of electronics ICs for automotive


UE Flag Logo FP7 Verdi Logo Participants R. Iskander, M.-M. Louerat, F. Pecheux
Durée 2011-2014
Partenaires Infineon, Fraunhofer Institute, Magillem Design Service, NXP, Continental (France & Allemagne)
Web Site Verdi Project

Verification for heterogeneous Reliable Design and Integration

Resume du projet Verdi

Robust FPGA

Logo ANR Participants H. Mehrez, R. Chotin-Avot
Durée 2011-2014
Partenaires Telecom ParisTech, TIMA
Web Site Projet Robust FPGA
Conception d'un FPGA tolérant aux défauts

Synchronisation dans les Systèmes sur Puce Complexes - Génération d'Horloge

Responsable: D. Galayko

Cette activité adresse les défis de génération d'horloge dans les systèmes sur puce numériques complexes. Démarrée en 2006 à CIAN, elle a été financée par l'ANR à travers les projets HODISS (2007-2010) et HERODOTOS (2010-2014). Les partenaires de cette activité sont CEA-LETI, Supélec et Ecole Centrale de Lyon (laboratoire Ampère).

SPACES - Security Evaluation of Physically Attacked Cryptoprocessors in Embedded Systems

Logo ANR Logo JST Participants P. Bazargan-Sabet
Durée 2011-2014



Tohuku University (coordinateur), Kobe University, University of Electro-Communications Tokyo, National Institute of Advanced Industrial Science and Technology
France TeleCom-ParisTech (coordinateur), SAFRAN-Morpho
Web Site Projet Spaces

ASTECAS - A SofTwarE defined radio receiver based on a Configurable DSP and An RF Sigma-Delta ADC

Logo ANR Participants H. Mehrez, H. Aboushady
Durée 2010-2013
Partenaires FlexRAS Technology, ITESM, CINVESTAV
Web Site Projet ASTECAS

SESAM - Smart multi-source Energy Scavenger for Autonomous Microsystems

Logo ANR Participants D. Galayko
Durée 2008-2011
Mise en oeuvre d'une source d'électricité puisant l'énergie dans son environnement immédiat

WASABI : Wireless system And SystemC-AMS, Basic Infrastructure

Logo ANR Participants M.-M. Louerat, H. Aboushady, F. Pecheux
Durée 2007-2010
Partenaires IEMN, ST Microelectronics, Magillem Design Systems