[12] | 1 | % les objectifs scientifiques/techniques du projet. |
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[33] | 2 | The objectives of the COACH project are to develop a complete framework to HPC |
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[20] | 3 | (accelerating solutions for existing software applications) and embedded |
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| 4 | applications (implementing an application on a low power standalone |
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[24] | 5 | device). The design steps are presented figure~\ref{coach-flow}. |
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[12] | 6 | \begin{figure}[hbtp]\leavevmode\center |
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| 7 | \includegraphics[width=.8\linewidth]{flow} |
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[182] | 8 | \caption{\label{coach-flow} COACH design flow} |
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[12] | 9 | \end{figure} |
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| 10 | \begin{description} |
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[104] | 11 | \item[HPC setup:] During this step, the user splits the application into 2 parts: the host application |
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| 12 | which remains on a PC and the SoC application which is mapped on the FPGA. |
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[235] | 13 | COACH will allow to automatically translate high level language programs to FPGA configurations. |
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| 14 | In addition, it will provide a SystemC simulation model of the whole system (PC+communication+FPGA-SoC) |
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| 15 | which will allow performance evaluation of the partitioning. |
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[104] | 16 | \item[SoC design:] In this phase, |
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[235] | 17 | COACH will allow the user to obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description. |
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| 18 | This description will consist of a process network corresponding to the application, |
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[12] | 19 | an OS, an instance of a generic hardware platform |
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[235] | 20 | and a mapping of processes on the platform components. COACH will offer different targets to map the processes: |
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[12] | 21 | software (the process runs on a SoC processor), |
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[99] | 22 | ASIP (the process runs on a SoC processor enhanced with dedicated instructions), |
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| 23 | and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus). |
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[235] | 24 | \item[Application compilation:] Once the SoC description is validated through performances analysis, COACH will generate automatically |
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[33] | 25 | an FPGA bitstream containing the hardware platform with the SoC application software and |
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[182] | 26 | an executable containing the host application. The user will be able to launch the application by |
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[33] | 27 | loading the bitstream on an FPGA and running the executable on PC. |
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[12] | 28 | \end{description} |
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| 29 | |
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| 30 | % l'avancee scientifique attendue. Preciser l'originalite et le caractere |
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| 31 | % ambitieux du projet. |
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[104] | 32 | %FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire} |
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[12] | 33 | |
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[182] | 34 | %The main scientific contribution of the project is to unify various synthesis techniques |
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| 35 | %(same input and output formats) allowing the user to swap without engineering effort |
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| 36 | %from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis. |
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| 37 | %Another advantage of this framework is to provide different abstraction levels from |
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| 38 | %a single description. |
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| 39 | %Finally, this description is device family independent and its hardware implementation |
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| 40 | %is automatically generated. |
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| 41 | |
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[12] | 42 | % Detailler les verrous scientifiques et techniques a lever par la realisation du projet. |
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[235] | 43 | System design is a very complex task and in this project we will try to simplify it |
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| 44 | as much as possible. For this purpose the following scientific and technological barriers |
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| 45 | have to be addressed. |
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| 46 | |
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| 47 | \begin{description} |
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| 48 | \item[Design Space Exploration:] |
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| 49 | The COACH environment will allow to easily map an application described by using a process |
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| 50 | network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will |
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| 51 | allow to explore the design space by allowing system designer to select and |
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| 52 | parameterize the target architecture, and to define the best hardware/software |
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| 53 | partitioning of the application. |
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| 54 | \item[Hardware Accelerators Synthesis (HAS):] |
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| 55 | COACH will allow the automatic generation of hardware accelerators when required. |
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| 56 | Hence, High-Level Synthesis (HLS) tools, Application Specific Instruction Processor |
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| 57 | (ASIP) design environment and source-level transformation tools (loop transformations |
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| 58 | and memory optimisation) will be provided. |
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| 59 | This will allow further exploration of the micro-architectural design space. |
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| 60 | HLS tools are sensitive to the coding style of the input specification and the domain |
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| 61 | they target (control vs. data dominated). |
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| 62 | The HLS tools of COACH will support a common language and coding style to avoid |
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| 63 | re-engineering by the designer. |
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| 64 | \item[Platform based design:] |
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| 65 | COACH will handle both \altera and \xilinx FPGA devices. |
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| 66 | COACH will define architectural templates that can be customized by adding |
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| 67 | dedicated coprocessors and ASIPs and by fixing template parameters such as |
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| 68 | the number of embedded processors, the number of sizes of embedded memory banks |
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| 69 | or the embedded the operating system. |
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| 70 | However, the specification of the application will be independant of both the |
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| 71 | architectural template and the target FPGA device. |
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| 72 | Basically, the 3 following architectural templates will be provided: |
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| 73 | \begin{enumerate} |
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| 74 | \item A \mustbecompleted{FIXME :: Neutral est tres pejoratif. Technology inependent, independant, standard ???} Neutral architectural template based on the SoCLib IP core library and the |
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| 75 | VCI/OCP communication infrastructure. |
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| 76 | \item An \altera architectural template based on the \altera IP core library, the |
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| 77 | AVALON system bus and the NIOS processor. |
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| 78 | \item A \xilinx architectural template based on the Xilinx IP core library, the PLB |
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| 79 | system bus and the Microblaze processor. |
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| 80 | \end{enumerate} |
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| 81 | \item[Hardware/Software communication middleware:] |
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| 82 | COACH will implement an homogeneous HW/SW communication infrastructure and |
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| 83 | communication APIs (Application Programming Interface), that will be used for |
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| 84 | communications between software tasks running on embedded processors and |
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| 85 | dedicated hardware coprocessors. |
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| 86 | \end{description} |
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| 87 | |
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| 88 | |
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| 89 | |
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| 90 | ---------------------------------------------------------------------------------------------- |
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| 91 | |
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| 92 | |
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[12] | 93 | \begin{itemize} |
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| 94 | \item HLS tools are sensitive to the style in which the algorithm is written. |
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| 95 | In addition, they are are not integrated into an architecture and system |
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[182] | 96 | exploration tool. Consequently, engineering work is required to swap from a tool to another, |
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[12] | 97 | to integrate the resulting simulation model to an architectural exploration tool |
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| 98 | and to synthesize the generated RTL description. |
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| 99 | %CA Additionnal preprocessing, source-level transformations, are thus |
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| 100 | %CA required to improve the process. |
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| 101 | %CA Particularly, this includes parallelism exposure and efficient memory mapping. |
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| 102 | \item Most HLS tools translate a sequential algorithm into a coprocessor |
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| 103 | containing a single data-path and finite state machine (FSM). In this way, |
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| 104 | only the fine grained parallelism is exploited (ILP parallelism). |
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| 105 | The challenge is to identify the coarse grained parallelism and to generate, |
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| 106 | from a sequential algorithm, coprocessor containing multiple communicating |
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[33] | 107 | tasks (data-paths and FSMs). To this aim, one may adapt techniques which |
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| 108 | were developed in the 1990 for the construction of distributed programs. |
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| 109 | However, in the context of HLS, there are still several original problems |
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| 110 | to be solved, mainly to do with the construction of FIFO communication |
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| 111 | channels and with memory optimization. |
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[104] | 112 | \item The COACH design flow has a top-down approach. In such a case, |
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| 113 | the required performance of a coprocessor (clock frequency, maximum cycles for |
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| 114 | a given computation, power consumption, etc) are imposed by the other system |
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| 115 | components. The challenge is to allow user to control accurately the synthesis |
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| 116 | process. For instance, the clock frequency must not be a result of the RTL synthesis |
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| 117 | but a strict synthesis constraint. |
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| 118 | \item The main problem in HPC is the communication between the PC and the SoC. |
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| 119 | This problem has 2 aspects. The first one is the run-time efficiency. The second is |
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| 120 | its engineering cost, especially if one want to refine an implementation |
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| 121 | at several abstract levels. |
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[33] | 122 | |
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[12] | 123 | \end{itemize} |
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| 124 | |
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| 125 | %Presenter les resultats escomptes en proposant si possible des criteres de reussite |
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| 126 | %et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en |
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| 127 | %fin de projet. |
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| 128 | The main result is the framework. It is composed concretely of: |
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[99] | 129 | a communication middleware for HPC, |
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| 130 | 5 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, |
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[12] | 131 | Memory optimisation HLS and ASIP), |
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[99] | 132 | 3 architectural templates that are synthesizable and that can be prototyped, |
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[12] | 133 | one design space exploration tool, |
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[235] | 134 | 2 operating systems (DNA/OS and MUTEKH). |
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[12] | 135 | \\ |
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[99] | 136 | The framework fonctionality will be demonstrated with the demonstrators |
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| 137 | (see task-7 page~\pageref{task-7}) and the tutorial example (see task-8 |
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[235] | 138 | page~\ref{subtask-tutorial}). |
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