Changeset 104 for anr/section-3.2.tex

Timestamp:

Feb 8, 2010, 9:17:37 AM (14 years ago)

Author:

coach

Message:

pc

File:

• anr/section-3.2.tex (modified) (5 diffs)

anr/section-3.2.tex

@@ -9 +9 @@
 \end{figure}
 \begin{description}
-\item[HPC setup] Here the user splits the application into 2 parts: the host application
-which remains on a PC and the SoC application which migrates into a SoC. 
-The framework provides a simulation model which allows an evaluation of the partitioning.
-\item[SoC design] In this phase, 
+\item[HPC setup:] During this step, the user splits the application into 2 parts: the host application
+which remains on a PC and the SoC application which is mapped on the FPGA. 
+The COACH framework provides a SystemC simulation model of the whole system (PC+communication+FPGA-SoC) which allows a performance evaluation of the partitioning.
+\item[SoC design:] In this phase, 
 the user can obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description.  
 This description consists of a process network corresponding to the SoC application, 
@@ -20 +20 @@
 ASIP (the process runs on a SoC processor enhanced with dedicated instructions),
 and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus).
-\item[Application compilation] Once the SoC description is validated, COACH generates automatically
+\item[Application compilation:] Once the SoC description is validated, COACH generates automatically
 an FPGA bitstream containing the hardware platform with the SoC application software and 
 an executable containing the host application. The user can launch the application by
@@ -28 +28 @@
 % l'avancee scientifique attendue. Preciser l'originalite et le caractere 
 % ambitieux du projet. 
+%FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire}
 The main scientific contribution of the project is to unify various synthesis techniques
 (same input and output formats) allowing the user to swap without engineering effort
-from one to another and even to chain them. for instance, it will be possible to run loop transformations before synthesis.
+from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis.
 Another advantage of this framework is to provide different abstraction levels from
 a single description.
@@ -41 +42 @@
 and technological barriers.
 \begin{itemize}
-\item The main problem in HPC is the communication between the PC and the SoC.
-This problem has 2 aspects. The first one is the run-time efficiency. The second is its engineering  cost, especially if one want to refine an implementation
-at several abstract levels.
-\item The COACH design flow has a top-down approach. In such a case,
-the required performance of a coprocessor (clock frequency, maximum cycles for
-a given computation, power consumption, etc) are imposed by the other system
-components. The challenge is to allow user to control accurately the synthesis
-process. For instance, the clock frequency must not be a result of the RTL synthesis
-but a strict synthesis constraint.
 \item HLS tools are sensitive to the style in which the algorithm is written.
 In addition, they are are not integrated into an architecture and system 
@@ -69 +61 @@
 to be solved, mainly to do with the construction of FIFO communication
 channels and with memory optimization.
+\item The COACH design flow has a top-down approach. In such a case,
+the required performance of a coprocessor (clock frequency, maximum cycles for
+a given computation, power consumption, etc) are imposed by the other system
+components. The challenge is to allow user to control accurately the synthesis
+process. For instance, the clock frequency must not be a result of the RTL synthesis
+but a strict synthesis constraint.
+\item The main problem in HPC is the communication between the PC and the SoC.
+This problem has 2 aspects. The first one is the run-time efficiency. The second is 
+its engineering  cost, especially if one want to refine an implementation
+at several abstract levels.
 
 \end{itemize}