Changeset 99 for anr/section-3.2.tex
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- Feb 8, 2010, 12:11:05 AM (14 years ago)
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anr/section-3.2.tex
r71 r99 18 18 and a mapping of processes on the platform components. The supported mapping are 19 19 software (the process runs on a SoC processor), 20 XXXpeci(the process runs on a SoC processor enhanced with dedicated instructions),21 and hardware (the process runs into a coprocessor generated by HLS and plugged on the SoC bus).20 ASIP (the process runs on a SoC processor enhanced with dedicated instructions), 21 and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus). 22 22 \item[Application compilation] Once the SoC description is validated, COACH generates automatically 23 23 an FPGA bitstream containing the hardware platform with the SoC application software and … … 76 76 %fin de projet. 77 77 The main result is the framework. It is composed concretely of: 78 2 HPC communication schemes with their implementation,79 5 H LS tools (control dominated HLS, data dominated HLS, Coarse grained HLS,78 a communication middleware for HPC, 79 5 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, 80 80 Memory optimisation HLS and ASIP), 81 3 systemC based virtual prototyping environment extended with synthesizable 82 RTL IP cores (generic, ALTERA/NIOS/AVALON, XILINX/MICROBLAZE/OPB), 81 3 architectural templates that are synthesizable and that can be prototyped, 83 82 one design space exploration tool, 84 2 operating system (OS).83 2 operating systems (DNA/OS and MUTEK. 85 84 \\ 86 The framework fonctionality will be demonstrated with XXX-EXAMPLE1, XXX-EXAMPLE2 87 and XXX-EXAMPLE3 on 4 archictures (generic/XILINX, generic/ALTERA, 88 proprietary/XILINX, proprietary/ALTERA). 89 85 The framework fonctionality will be demonstrated with the demonstrators 86 (see task-7 page~\pageref{task-7}) and the tutorial example (see task-8 87 page~\ref{subtask-tutorial}.
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