[36] | 1 | \begin{figure}\leavevmode\center |
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| 2 | \definecolor{gtcBoxHeavy}{rgb}{0.10,0.10,0.90} |
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| 3 | \definecolor{gtcBoxLight}{rgb}{0.9,0.90,0.99} |
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| 4 | \definecolor{gtcTaskBG0} {rgb}{0.99,0.90,0.7} |
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| 5 | \definecolor{gtcTaskBG1} {rgb}{0.90,0.99,0.7} |
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| 6 | \definecolor{gtcMilestone}{rgb}{0.9,0.4,0.4} |
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| 7 | \immediate\write\ganttdata{ML=6 ML=12 ML=18 ML=24} |
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[34] | 8 | \def\ganttlabelstyle#1{\begin{small}#1\end{small}} |
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| 9 | \def\gantttitlestyle#1{\begin{scriptsize}\textit{#1}\end{scriptsize}} |
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[36] | 10 | \hspace*{-.6cm} |
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[34] | 11 | \input{gantt.tex} |
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[36] | 12 | \caption{\label{gantt}Gantt diagram of delivrables} |
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| 13 | \end{figure} |
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[34] | 14 | |
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[36] | 15 | The figure~\ref{gantt} presents the Gantt diagram of the project. |
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| 16 | Before the final release (T0+36), there are 4 milestones (red lines on the figure) at |
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| 17 | $T0+6$, $T0+12$, $T0+18$ and $T0+24$ that are rendez-vous points of the precedent |
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| 18 | delivrables. |
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| 19 | \begin{description} |
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| 20 | \item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of |
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[38] | 21 | demonstatrors as a reference software. |
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[36] | 22 | \item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are |
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[38] | 23 | written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC. |
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[36] | 24 | The main restrictions are: |
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| 25 | 1) only the COACH architectural template is supported, |
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[38] | 26 | 2) HAS is not available (but prototyping with virtual coprocessors is available), |
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| 27 | 3) Enhanced communication schemes are not available. |
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[36] | 28 | \item[Milestone 3 ($T0+18$)] The second COACH release. At this step most of the COACH |
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| 29 | features are availables. |
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| 30 | The main restriction is that COACH can not yet generate FPGA-SoC for ALTERA and XILINX |
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[38] | 31 | architectural templates. |
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[36] | 32 | The others restriction is that the HAS tools are not yet fully operational. |
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[38] | 33 | \item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is |
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[36] | 34 | supported. |
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| 35 | The main restriction are: |
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| 36 | 1) The HAS tools are not yet optimum, |
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| 37 | 2) dynamic reconfiguration is not supported, |
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| 38 | 3) \mustbecompleted{FIXME:ALL .....} |
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| 39 | \item[Final Release ($T0+36$)] |
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| 40 | \end{description} |
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| 41 | This organisation allows to advance globally the project step by step mixing development |
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| 42 | and demonstrator delivrables. |
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[38] | 43 | Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility |
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| 44 | at the integration phase is significantly reduced. |
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[36] | 45 | \par |
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| 46 | The project has several critical issues: |
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| 47 | \begin{description} |
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| 48 | \item[\xcoachplus format (\novers{\specXcoachDoc}, \novers{\specXcoachToC})] |
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[38] | 49 | Because all the HAS tools rely on it, it is a |
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[36] | 50 | crucial task. There are no work-arround but as mentionned in |
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[38] | 51 | section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) we have worked on it |
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| 52 | for a year and are confident. |
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[36] | 53 | \item[\xcoachplus format (\novers{\specXcoachDoc}, |
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| 54 | \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})] |
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[40] | 55 | Its aim is the generation of the coprocessors (hardware \& prototyping model). |
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| 56 | By centralizing the coprocessor generation, it guarantees their functioning |
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[36] | 57 | independently of the used HAS tools. |
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[38] | 58 | Our experience with UGH and GAUT give us confidence in the succes of this |
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| 59 | task. |
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[36] | 60 | \item[prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC}, |
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| 61 | {\csgXilinxSystemC}] |
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| 62 | The SocLib component library contains most of the SystemC models used for the |
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| 63 | prototyping description of the ALTERA and XILINX architectural templates. |
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[40] | 64 | Nevertheless, at this time we do not know how many are missing and if the existing |
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[36] | 65 | are really useables. |
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[40] | 66 | If the work of theses tasks is too important, they will be abandoned. |
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[36] | 67 | In this case the work-arround to prototype the XILINX and ALTERA architectural |
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| 68 | templates is to use the COACH one. These architectures being very similar, the |
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| 69 | simulation results must be proportional. Theses tasks will be changed by measuring |
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| 70 | the deviance. |
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| 71 | \item[VCI/AVALON \& VCI/PLB bridges (\novers{\hpcAvalonBridge}, \novers{\hpcPlbBridge})] |
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| 72 | If one of these tasks is impossible or too important or leads to inefficiency, |
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[40] | 73 | it will be abandoned. |
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[36] | 74 | In this case, the COACH architectural template will not be available for HPC and |
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| 75 | a SystemC VCI model corresponding to the PCI/X IP will be developped to allow |
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| 76 | prototyping. |
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| 77 | \end{description} |
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| 78 | |
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