Changeset 38 for anr/section-4.4.tex


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Timestamp:
Jan 19, 2010, 11:01:35 AM (14 years ago)
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coach
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  • anr/section-4.4.tex

    r36 r38  
    1919\begin{description}
    2020\item[Milestone 1 ($T0+6$)] Specification of COACH inputs, of the \xcoach format and of
    21     demonstatrors as a referennce software.
     21    demonstatrors as a reference software.
    2222\item[Milestone 2 ($T0+12$)] The first COACH release. At this step the demonstrators are
    23     written in COACH. The COACH release allows to prototype and to generate the FPGA-SoC.
     23    written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC.
    2424    The main restrictions are:
    2525    1) only the COACH architectural template is supported,
    26     2) HAS is not available (but prototyping with virtual coprocessor is available),
    27     3) Enhanced communication schems are not available.
     26    2) HAS is not available (but prototyping with virtual coprocessors is available),
     27    3) Enhanced communication schemes are not available.
    2828\item[Milestone 3 ($T0+18$)]  The second COACH release. At this step most of the COACH
    2929    features are availables.
    3030    The main restriction is that COACH can not yet generate FPGA-SoC for ALTERA and XILINX
    31     architectural template.
     31    architectural templates.
    3232    The others restriction is that the HAS tools are not yet fully operational.
    33 \item[Milestone 4 ($T0+24$)] The pre-rlease of the COACH project. The full design flow is
     33\item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is
    3434    supported.
    3535    The main restriction are:
     
    4141This organisation allows to advance globally the project step by step mixing development
    4242and demonstrator delivrables.
    43 So demonstrator feed-back will arrive early and so the risk to point out incompatibility
    44 at the integration phasis is suppressed.
     43Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility
     44at the integration phase is significantly reduced.
    4545\par
    4646The project has several critical issues:
    4747\begin{description}
    4848\item[\xcoachplus format (\novers{\specXcoachDoc}, \novers{\specXcoachToC})]
    49     Because it bonds tightly all the HAS tools, it is a
     49    Because all the HAS tools rely on it, it is a
    5050    crucial task. There are no work-arround but as mentionned in
    51     section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) we worked ont it since a
    52     year and are confident.
     51    section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) we have worked on it
     52        for a year and are confident.
    5353\item[\xcoachplus format (\novers{\specXcoachDoc},
    5454      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
    55     It aims with the generation of the coprocessors (hardware \& prototyping model),
    56     By centralizing the coprocessor generations, it guarantees their operating
     55    Its aim is the generation of the coprocessors (hardware \& prototyping model),
     56    By centralizing the coprocessor generation, it guarantees their operating
    5757    independently of the used HAS tools.
     58        Our experience with UGH and GAUT give us confidence in the succes of this
     59        task.
    5860\item[prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC},
    5961     {\csgXilinxSystemC}]
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