[26] | 1 | \begin{taskinfo} |
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| 2 | \let\UBS\leader |
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| 3 | \let\UPMC\enable |
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| 4 | \let\TIMA\enable |
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| 5 | \end{taskinfo} |
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| 6 | % |
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| 7 | \begin{objectif} |
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[56] | 8 | The objectives of this task are to provide the two HAS back-ends of the COACH project and |
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[40] | 9 | a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as given |
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[26] | 10 | by the processors and the BUS. |
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[40] | 11 | %pourquoi en majuscule? |
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[26] | 12 | \\ |
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[40] | 13 | The HAS back-ends as shown in figure~\ref{archi-hls} reads \xcoach data and provides |
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| 14 | \xcoachplus data, i.e. \xcoach data annotated with hardware information such as |
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| 15 | variables bindings to registers, operations bindings to cells and a schedule. The \xcoach format |
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[48] | 16 | being generated by \novers{\specXcoachToCA} deliverable and \xcoachplus being treated by |
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[36] | 17 | \novers{\specXcoachToSystemC} and \novers{\specXcoachToVhdl} deliverables, |
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[56] | 18 | this task is very dependent on task~1. |
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[26] | 19 | \par |
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| 20 | For the two HAS front-end, this task is based on the already existing HLS tools GAUT and |
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[40] | 21 | UGH. These tools are complementary and not in competition because they cover respectively |
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| 22 | data and control dominated designs. |
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[26] | 23 | The organization of the task is firstly to integrate quickly the existing HLS to the COACH |
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| 24 | framework. Secondly these tools will be improved to allows to treat data dominated application |
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[40] | 25 | with a few control for GAUT and control dominated application with a few data processing |
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[26] | 26 | for UGH. This will enlarge the domain the HLS can cover. |
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| 27 | \end{objectif} |
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| 28 | % |
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[52] | 29 | \begin{workpackage} |
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[26] | 30 | \item The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It |
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[56] | 31 | consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing |
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[26] | 32 | them by \xcoach and \xcoachplus drivers. |
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| 33 | \begin{livrable} |
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[57] | 34 | \itemL{6}{12}{x}{\Stima}{UGH integration}{12:0:0} |
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[98] | 35 | The UGH software that reads \xcoach format. |
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[52] | 36 | \itemV{12}{18}{x}{\Supmc}{UGH integration} |
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[98] | 37 | The UGH software that writes \xcoachplus format. |
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[52] | 38 | \itemL{18}{33}{x}{\Supmc}{UGH integration}{0:2:4.0} |
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| 39 | Maintenance work of the UGH software. |
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[26] | 40 | \end{livrable} |
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| 41 | \item The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It |
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| 42 | consists of suppressing the C commpiler and the SystemC and VHDL drivers and replacing |
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| 43 | them by \xcoach and \xcoachplus drivers. |
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| 44 | \begin{livrable} |
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[52] | 45 | \itemV{6}{12}{x}{\Subs}{GAUT integration} |
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| 46 | The GAUT software that is able to read \xcoach format. |
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| 47 | \itemV{12}{18}{x}{\Subs}{GAUT integration} |
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| 48 | The GAUT software that is able to read \xcoach format and to write \xcoachplus format. |
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| 49 | \itemL{18}{33}{x}{\Subs}{GAUT integration}{0:0:0} |
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| 50 | Maintenance work of the GAUT software. |
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[26] | 51 | \end{livrable} |
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| 52 | \item The goal of this \ST is to improve the UGH and GAUT HLS tools. |
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[76] | 53 | UGH and GAUT experimentations have shown respectively usefull enhancements. |
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[26] | 54 | \begin{livrable} |
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[57] | 55 | \itemL{18}{24}{x}{\Stima}{UGH enhancement 1}{0:9:0} |
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[52] | 56 | The UGH software whith support for treating automatically data dominated sections |
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| 57 | included into a control dominated application. |
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[57] | 58 | \itemL{21}{27}{x}{\Stima}{UGH enhancement 2}{0:3:6} |
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[52] | 59 | The UGH software that is able to generate a micro-architecture without the |
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| 60 | variable binding currently done by the designer. |
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| 61 | \itemL{6}{18}{x}{\Subs}{GAUT enhancement 1}{0:0:0} |
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| 62 | Release of the GAUT software that supports the control and data flow formal model. |
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[47] | 63 | \mustbecompleted{FIXME:USB ca ne va pas avec l'intro de la tache, UGH n'a |
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| 64 | plus aucune utilite si ceci reste} |
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[52] | 65 | \itemL{18}{30}{x}{\Subs}{GAUT enhancement 2}{0:0:0} |
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| 66 | Release of the GAUT software that supports the control and data flow formal model |
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| 67 | and also supports new constraints and objectives defined in |
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| 68 | \mustbecompleted{FIXME:USB utilise une macro svp: \ST1-1} |
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| 69 | \mustbecompleted{FIXME:UBS: quel delivrable ??}. |
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[76] | 70 | \itemV{6}{18}{d}{\Subs}{Design Space Exploration}{0:0:0} |
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| 71 | \mustbecompleted{FIXME:UBS GAUT enhancement 3 serait peut-etre meilleur} |
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| 72 | Specification of a Design Space Exploration framework for the HAS Back-end: |
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| 73 | The high level specification tools, such as GAUT, have to be able to use synthesis feed-back |
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| 74 | informations in order to explore the design space and to generate optimized architectures. |
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| 75 | \itemL{18}{30}{x}{\Subs}{Design Space Exploration}{0:0:0} |
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| 76 | Release of the GAUT software that supports the features defined in \ST ????. |
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[26] | 77 | \end{livrable} |
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| 78 | \item In FPGA-SoC, the frequency is given by the processors and the BUS. The coprocessors |
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| 79 | generated by HLS synthesis must respect this frequency. However, the HLS tools can not |
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[40] | 80 | guarantee that the micro-architectures they generate accurately respect this |
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[26] | 81 | frequency. This is especially the case when the target is a FPGA device, because the |
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| 82 | delays are really known only after the RTL synthesis and that estimated delays used |
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[40] | 83 | by the HLS are very imprecize. The goal of this \ST is to provide a tool to adapt |
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[26] | 84 | the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL |
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| 85 | synthesis. |
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| 86 | \begin{livrable} |
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[52] | 87 | \itemV{0}{12}{d}{\Supmc}{frequency calibration} |
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| 88 | A document describing the set up of the coprocessor frequency calibration. |
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| 89 | \itemV{12}{24}{x}{\Supmc}{frequency calibration} |
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| 90 | A VHDL description of hardware added to the coprocessor to enable the calibration. |
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| 91 | \itemL{24}{33}{x}{\Supmc}{frequency calibration}{2:.5:3.5} |
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| 92 | The frequency calibration software consists of a driver in the FPGA-SoC operating |
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| 93 | system and of a control software on a PC. |
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[26] | 94 | \end{livrable} |
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| 95 | \end{workpackage} |
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