Changeset 40 for anr/task-4.tex

Timestamp:

Jan 19, 2010, 5:03:37 PM (14 years ago)

Author:

coach

Message:

Paul task 4 to 6 and section 4.4

File:

• anr/task-4.tex (modified) (3 diffs)

anr/task-4.tex

@@ -6 +6 @@
 %
 \begin{objectif}
-This objectives of this task are to provides the 2 HAS back-ends of the COACH project and
-a tool that adapt the coprocessor frequency to the FPGA-SoC frequency. This later is given
+The objectives of this task are to provide the 2 HAS back-ends of the COACH project and
+a tool that adapt the coprocessor frequency to the FPGA-SoC frequency as given 
 by the processors and the BUS.
+%pourquoi en majuscule?
 \\
-The HAS back-ends as shown figure~\ref{archi-hls} reads \xcoach data and provides
-\xcoachplus data that is \xcoach format annotated with hardware information such as
-variable binded on register, operation binded on cell and sheduled. The \xcoach format
+The HAS back-ends as shown in figure~\ref{archi-hls} reads \xcoach data and provides
+\xcoachplus data, i.e. \xcoach data annotated with hardware information such as
+variables bindings to registers, operations bindings to cells and a schedule. The \xcoach format
 being generated by {\specXcoachToC} deliverable and \xcoachplus being treated by
 \novers{\specXcoachToSystemC} and \novers{\specXcoachToVhdl} deliverables,
-this task is very dependent of the task~1.
+this task is very dependen on task~1.
 \par
 For the two HAS front-end, this task is based on the already existing HLS tools GAUT and
-tools. These tools are complementary and not competitor because they cover irespectively
-data and control dominated orthogonal domain.
+UGH. These tools are complementary and not in competition because they cover respectively
+data and control dominated designs.
 The organization of the task is firstly to integrate quickly the existing HLS to the COACH
 framework. Secondly these tools will be improved to allows to treat data dominated application
-with a few control for GAUT and control dominated application with a few data treatment
+with a few control for GAUT and control dominated application with a few data processing
 for UGH. This will enlarge the domain the HLS can cover.
 \end{objectif}
@@ -53 +54 @@
         automatically data dominated sections included into a control dominated application.
     \item{}{21}{27}{x}{\Stima}{UGH enhancement 2} The UGH software that is able to
-        generate an micro-architecture without the variable binding currently done by the
+        generate a micro-architecture without the variable binding currently done by the
         designer.
     \item{}{18}{24}{x}{\Subs}{GAUT enhancement 1} A GAUT excutable that is able to
@@ -64 +65 @@
 \item In FPGA-SoC, the frequency is given by the processors and the BUS. The coprocessors
     generated by HLS synthesis must respect this frequency. However, the HLS tools can not
-    guarantee that the micro-architectures they generate, respect accurately this
+    guarantee that the micro-architectures they generate accurately respect this
     frequency. This is especially the case when the target is a FPGA device, because the
     delays are really known only after the RTL synthesis and that estimated delays used
-    by the HLS are very imprecis. The goal of this \ST is to provide a feature to adapt
+    by the HLS are very imprecize. The goal of this \ST is to provide a tool to adapt
     the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL
     synthesis.