1 | \begin{taskinfo} |
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2 | \let\UPMC\leader |
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3 | \let\TIMA\enable |
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4 | \let\ALTERA\enable |
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5 | \end{taskinfo} |
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6 | % |
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7 | \begin{objectif} |
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8 | This task pools the features dedicated to HPC system design. It is described on |
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9 | figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in |
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10 | \begin{itemize} |
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11 | \item Helping the HPC designer to find a good partition of the initial application |
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12 | (figure~\ref{archi-hpc}. |
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13 | \item Providing communication schemes between the software part runing on the PC and the |
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14 | FPGA-SoC. |
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15 | \item Implementing the communication scheme at all levels: partition help, software |
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16 | implementation both on the PC and in the operating system of the FPGA-SoC, hardware. |
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17 | \item FPGA reconfiguration. \mustbecompleted{FIXME:TIMA} |
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18 | \end{itemize} |
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19 | The low level hardware transmission support will be the PCI/X bus which allows high bit-rate |
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20 | transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for |
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21 | their FPGA and that GPU HPC softwares use also it. |
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22 | This will allow us at least to be inspired by GPU communication schemes and may be to reuse |
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23 | parts of the GPU softwares. |
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24 | \end{objectif} |
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25 | % |
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26 | \begin{workpackage}{D5} |
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27 | \item This \ST is the definition of the communication schemes as a software API |
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28 | (Application Programing Interface) between the application part running on the PC and |
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29 | the application part running on the FPGA-SoC. |
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30 | \begin{livrable} |
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31 | \item{}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API. |
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32 | \global\edef\hpcCommApi{\name} |
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33 | \end{livrable} |
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34 | \item This \ST aims consists in helping the application partitioning help. |
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35 | It is a library implementing the communication API with features to profile |
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36 | the application partionning. |
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37 | \begin{livrable} |
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38 | \item{}{6}{12}{x}{\Supmc}{HPC partionning helper} A library implementing the communication |
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39 | API defined in the {\hpcCommApi} delivrable. |
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40 | \end{livrable} |
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41 | \item This \ST aims with the implementation of the communication API on the both sides (PC |
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42 | part and FPGA-SoC). |
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43 | \begin{livrable} |
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44 | \item{}{12}{21}{x}{\Supmc}{HPC API for Linux PC} The PC part of the HPC communication API |
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45 | that comminicate with the FPGA-SOC, a library and probably a LINUX module. |
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46 | \item{}{12}{21}{x}{\Supmc}{HPC API for MUTEK OS} The FPGA-SoC part of the communication API, a |
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47 | driver.\global\edef\hpcMutekDriver{\name} |
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48 | \item{}{21}{24}{x}{\Stima}{HPC API for DNA OS} Port of the {\hpcMutekDriver} driver on the DNA OS. |
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49 | \end{livrable} |
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50 | \item This \ST aims with the implementation of hardware required by the COACH |
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51 | architectural template for using the PCI/X IP of \altera and \xilinx. |
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52 | \begin{livrable} |
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53 | \item{}{9}{18}{h}{\Stima}{HPC hardware \xilinx} |
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54 | \setMacroInAuxFile{hpcPlbBridge} |
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55 | The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model. |
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56 | \item{}{9}{18}{h}{\Saltera}{HPC hardware \altera} |
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57 | \setMacroInAuxFile{hpcAvalonBridge} |
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58 | The synthesizable VHDL description of a AVALON/VCI bridge and its corresponding SystemC model. |
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59 | \end{livrable} |
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60 | \item This \ST aims with the dynamic reconfiguration of FPGA. |
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61 | \begin{livrable} |
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62 | \item{}{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers} |
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63 | \global\edef\hpcDynconfDriver{\name} |
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64 | \mustbecompleted{FIXME:TIMA ....} |
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65 | \item{}{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers} |
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66 | Port of the {\hpcDynconfDriver} \mustbecompleted{FIXME:TIMA driver} on the MUTEK OS. |
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67 | \item{}{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration} |
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68 | \mustbecompleted{FIXME:TIMA ....} |
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69 | \item{}{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration} |
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70 | \mustbecompleted{FIXME:TIMA ....} |
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71 | \end{livrable} |
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72 | \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board |
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73 | with its PCI/X IP. These boards are dedicated to the COACH HPC development. |
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74 | They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT. |
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75 | \begin{livrable} |
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76 | \item{}{0}{6}{m}{\Saltera}{HPC development boards} Two PCI/X FPGA boards. |
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77 | \end{livrable} |
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78 | \end{workpackage} |
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