Changeset 104
- Timestamp:
- Feb 8, 2010, 9:17:37 AM (15 years ago)
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anr/section-3.2.tex
r99 r104 9 9 \end{figure} 10 10 \begin{description} 11 \item[HPC setup ] Herethe user splits the application into 2 parts: the host application12 which remains on a PC and the SoC application which migrates into a SoC.13 The framework provides a simulation model which allows anevaluation of the partitioning.14 \item[SoC design ] In this phase,11 \item[HPC setup:] During this step, the user splits the application into 2 parts: the host application 12 which remains on a PC and the SoC application which is mapped on the FPGA. 13 The COACH framework provides a SystemC simulation model of the whole system (PC+communication+FPGA-SoC) which allows a performance evaluation of the partitioning. 14 \item[SoC design:] In this phase, 15 15 the user can obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description. 16 16 This description consists of a process network corresponding to the SoC application, … … 20 20 ASIP (the process runs on a SoC processor enhanced with dedicated instructions), 21 21 and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus). 22 \item[Application compilation ] Once the SoC description is validated, COACH generates automatically22 \item[Application compilation:] Once the SoC description is validated, COACH generates automatically 23 23 an FPGA bitstream containing the hardware platform with the SoC application software and 24 24 an executable containing the host application. The user can launch the application by … … 28 28 % l'avancee scientifique attendue. Preciser l'originalite et le caractere 29 29 % ambitieux du projet. 30 %FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire} 30 31 The main scientific contribution of the project is to unify various synthesis techniques 31 32 (same input and output formats) allowing the user to swap without engineering effort 32 from one to another and even to chain them. for instance, it will be possible to run loop transformations before synthesis.33 from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis. 33 34 Another advantage of this framework is to provide different abstraction levels from 34 35 a single description. … … 41 42 and technological barriers. 42 43 \begin{itemize} 43 \item The main problem in HPC is the communication between the PC and the SoC.44 This problem has 2 aspects. The first one is the run-time efficiency. The second is its engineering cost, especially if one want to refine an implementation45 at several abstract levels.46 \item The COACH design flow has a top-down approach. In such a case,47 the required performance of a coprocessor (clock frequency, maximum cycles for48 a given computation, power consumption, etc) are imposed by the other system49 components. The challenge is to allow user to control accurately the synthesis50 process. For instance, the clock frequency must not be a result of the RTL synthesis51 but a strict synthesis constraint.52 44 \item HLS tools are sensitive to the style in which the algorithm is written. 53 45 In addition, they are are not integrated into an architecture and system … … 69 61 to be solved, mainly to do with the construction of FIFO communication 70 62 channels and with memory optimization. 63 \item The COACH design flow has a top-down approach. In such a case, 64 the required performance of a coprocessor (clock frequency, maximum cycles for 65 a given computation, power consumption, etc) are imposed by the other system 66 components. The challenge is to allow user to control accurately the synthesis 67 process. For instance, the clock frequency must not be a result of the RTL synthesis 68 but a strict synthesis constraint. 69 \item The main problem in HPC is the communication between the PC and the SoC. 70 This problem has 2 aspects. The first one is the run-time efficiency. The second is 71 its engineering cost, especially if one want to refine an implementation 72 at several abstract levels. 71 73 72 74 \end{itemize}
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