Changeset 108
- Timestamp:
- Feb 8, 2010, 10:13:09 AM (15 years ago)
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anr/task-2.tex
r74 r108 12 12 This task consists of 13 13 \begin{itemize} 14 \item the development of all the missing components (SytemC model and/or synthesizable VHDL description), 15 \item the configuration and the development of drivers of the operating systems, 16 \item the CSG software that generates the simulators for prototyping and the FPGA-SoC system, 17 \item the specification of enhanced communication schemes and their sofware and hardware implementation. 14 \item the development of all the missing components (SytemC models and/or synthesizable VHDL models 15 of the IP-cores), 16 \item the configuration and the development of drivers %FIXME == {driver de quoi ???} 17 of the operating systems, 18 \item the CSG software that generates the SystemC simulators for prototyping and the synthesizable description 19 of the FPGA-SoC system (i.e. its bitstream), %FIXME == {VHDL ou bitstream ???} 20 \item the specification of enhanced communication schemes and their sofware and hardware implementations. 18 21 \end{itemize} 19 22 This task being based on the SocLib platform, a first release will be delivrable at $T0+12$ … … 27 30 \begin{livrable} 28 31 \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch} 29 \mustbecompleted{FIXME: LIP6 :: Pas clair pour un non expert du projet... ET remplacement de "milestone" par 30 "CSG release"} 31 The first milestone that will allow demonstrators to start working using the COACH 32 The first software release of the CSG tool that will allow demonstrators to start working by using the COACH 32 33 hardware architecture template. 33 34 \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly} … … 36 37 In this milestone only the SystemC prototyping will be supported for the XILINX 37 38 and ALTERA architectural template. 38 HAS is available. 39 HAS is available. %FIXME = {ca veut dire ???} 39 40 \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch} 40 41 This milestone extends CSG (\csgPrototypingOnly) to … … 43 44 Maintenance work of CSG. 44 45 \end{livrable} 45 \item This \ST deals with the components of the architectural template .46 \item This \ST deals with the components of the architectural templates. 46 47 \\ 47 48 For the COACH architectural template, it consists of the devlopment of the VHDL 48 synthesizable description of the missing components. Notice that the SystemC models 49 synthesizable description of the missing components. %FIXME == {pas clair missing components} 50 Notice that the SystemC models 49 51 comes from the SocLib ANR project, the processor with its cache comes from the TSAR 50 52 ANR project. 51 53 \\ 52 For the XILINX and ALTERA architectural template , we use the XILINX and ALTERA IPs.54 For the XILINX and ALTERA architectural templates, we use the XILINX and ALTERA IPs (NIOS, Microblaze, memories, busses...). 53 55 The missing component is the MWMR used for communication between the tasks of the 54 56 application. … … 60 62 The SystemC simulation module of the MWMR component with a PLB bus interface plus 61 63 the SystemC modules of the components of the XILINX architectural template 62 not available in the SocLib component library.64 currently not available in the SocLib component library. 63 65 \itemL{18}{24}{h}{\Stima}{XILINX architecture}{9:9:0} 64 66 The synthesizable VHDL description of the MWMR component corresponding to the … … 68 70 The SystemC simulation module of the MWMR component with an AVALON bus interface plus 69 71 the SystemC modules of the components of the ALTERA architectural template 70 not available in the SocLib component library.72 currently not available in the SocLib component library. 71 73 \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{0:0:0} 72 74 The synthesizable VHDL description of the MWMR component corresponding to the … … 86 88 system and the development of drivers for the hardware architectural templates 87 89 and enhanced communication schemes defined in \novers{\specCsgManual} delivrable. 88 For the ALTERA and XILINX architectural template , the OSs must also be ported on90 For the ALTERA and XILINX architectural templates, the OSs must also be ported on 89 91 the NIOS2 and MICROBLAZE processors. 90 92 \begin{livrable} 91 93 \itemV{6}{8}{x}{\Supmc}{MUTEK OS} 92 The drivers required for the first CSG milestone (delivrable \csgCoachArch). 94 The drivers %FIXME = {???} 95 required for the first CSG milestone (delivrable \csgCoachArch). 93 96 \itemV{8}{18}{x}{\Supmc}{MUTEK 0S} 94 97 The drivers required for the second CSG milestone ({\csgPrototypingOnly}). … … 96 99 Maintenance work. 97 100 \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0} 98 Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.101 Porting of MUTEK OS on the NIOS2 and MICROBLAZE processors. 99 102 \itemV{6}{8}{x}{\Stima}{DNA OS} 100 103 The drivers required for the first CSG milestone (delivrable \csgCoachArch). … … 104 107 Maintenance work. 105 108 \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{3:1:0} 106 Port of DNA OS on the NIOS2 and MICROBLAZE processors.109 Porting of DNA OS on the NIOS2 and MICROBLAZE processors. 107 110 \end{livrable} 108 111 \end{workpackage}
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