Changeset 109

Timestamp:

Feb 8, 2010, 11:52:14 AM (14 years ago)

Author:

coach

Message:

pc

File:

• anr/task-3.tex (modified) (3 diffs)

anr/task-3.tex

@@ -8 +8 @@
 an hardware accelerator, which must be written in a familiar language
 (C/C++) with as few constraints as possible, into a form suitable for
-the HLS tools. If the target is an ASIP, the frontend has to extract 
+the HLS tools (i.e. HAS back-end tools of the COACH project). If the 
+target is an ASIP, the frontend has to extract 
 patterns from the source code and convert them into the definition
 of an extensible processor. If the target is a process network, the
@@ -14 +15 @@
 as possible, identify communication channels, and output an \xcoach
 description.
+%FIXME == {Impossible d'utiliser les transformations de boucles pour amélierer la partie SW ??? }
 \end{objectif}
 %
@@ -62 +64 @@
     \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
       Description of the process network construction method for programs with 
-      polyhedral loops. User manual.
+      polyhedral loops. User manual. %FIXME == {User manual ou Specification. Si user manual alors le mettre en dissemination}
     \itemL{30}{36}{d}{\Slip}{Process generation method}{0:0:0}
       Final assessment of the method and improved version of the user manual.
+      %FIXME == {User manual ou Specification. Si user manual alors le mettre en dissemination}
     \itemV{6}{12}{x}{\Slip}{Process construction)}
       Preliminary implementation in the Syntol framework.