- Timestamp:
- Feb 8, 2010, 11:52:14 AM (15 years ago)
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anr/task-3.tex
r95 r109 8 8 an hardware accelerator, which must be written in a familiar language 9 9 (C/C++) with as few constraints as possible, into a form suitable for 10 the HLS tools. If the target is an ASIP, the frontend has to extract 10 the HLS tools (i.e. HAS back-end tools of the COACH project). If the 11 target is an ASIP, the frontend has to extract 11 12 patterns from the source code and convert them into the definition 12 13 of an extensible processor. If the target is a process network, the … … 14 15 as possible, identify communication channels, and output an \xcoach 15 16 description. 17 %FIXME == {Impossible d'utiliser les transformations de boucles pour amélierer la partie SW ??? } 16 18 \end{objectif} 17 19 % … … 62 64 \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition} 63 65 Description of the process network construction method for programs with 64 polyhedral loops. User manual. 66 polyhedral loops. User manual. %FIXME == {User manual ou Specification. Si user manual alors le mettre en dissemination} 65 67 \itemL{30}{36}{d}{\Slip}{Process generation method}{0:0:0} 66 68 Final assessment of the method and improved version of the user manual. 69 %FIXME == {User manual ou Specification. Si user manual alors le mettre en dissemination} 67 70 \itemV{6}{12}{x}{\Slip}{Process construction)} 68 71 Preliminary implementation in the Syntol framework.
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