Changeset 108 for anr

Timestamp:

Feb 8, 2010, 10:13:09 AM (15 years ago)

Author:

coach

Message:

pc

File:

• anr/task-2.tex (modified) (9 diffs)

anr/task-2.tex

@@ -12 +12 @@
 This task consists of
 \begin{itemize}
-\item the development of all the missing components (SytemC model and/or synthesizable VHDL description),
-\item the configuration and the development of drivers of the operating systems,
-\item the CSG software that generates the simulators for prototyping and the FPGA-SoC system,
-\item the specification of enhanced communication schemes and their sofware and hardware implementation.
+\item the development of all the missing components (SytemC models and/or synthesizable VHDL models 
+of the IP-cores),
+\item the configuration and the development of drivers %FIXME == {driver de quoi ???}
+of the operating systems,
+\item the CSG software that generates the SystemC simulators for prototyping and the synthesizable description 
+of the FPGA-SoC system (i.e. its bitstream), %FIXME == {VHDL ou bitstream ???}
+\item the specification of enhanced communication schemes and their sofware and hardware implementations.
 \end{itemize}
 This task being based on the SocLib platform, a first release will be delivrable at $T0+12$
@@ -27 +30 @@
     \begin{livrable}
     \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
-        \mustbecompleted{FIXME: LIP6 :: Pas clair pour un non expert du projet... ET remplacement de "milestone" par
-    "CSG release"} 
-        The first milestone that will allow demonstrators to start working using the COACH
+        The first software release of the CSG tool that will allow demonstrators to start working by using the COACH
         hardware architecture template.
     \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
@@ -36 +37 @@
         In this milestone only the SystemC prototyping will be supported for the XILINX
         and ALTERA architectural template.
-        HAS is available.
+        HAS is available. %FIXME = {ca veut dire ???}
     \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
         This milestone extends CSG (\csgPrototypingOnly) to
@@ -43 +44 @@
         Maintenance work of CSG.
     \end{livrable}
-\item This \ST deals with the components of the architectural template.
+\item This \ST deals with the components of the architectural templates.
     \\
     For the COACH architectural template, it consists of the devlopment of the VHDL
-    synthesizable description of the missing components. Notice that the SystemC models
+    synthesizable description of the missing components. %FIXME == {pas clair missing components} 
+    Notice that the SystemC models
     comes from the SocLib ANR project, the processor with its cache comes from the TSAR
     ANR project.
     \\
-    For the XILINX and ALTERA architectural template, we use the XILINX and ALTERA IPs.
+    For the XILINX and ALTERA architectural templates, we use the XILINX and ALTERA IPs (NIOS, Microblaze, memories, busses...).
     The missing component is the MWMR used for communication between the tasks of the
     application.
@@ -60 +62 @@
         The SystemC simulation module of the MWMR component with a PLB bus interface plus
         the SystemC modules of the components of the XILINX architectural template
-        not available in the SocLib component library.
+        currently not available in the SocLib component library.
     \itemL{18}{24}{h}{\Stima}{XILINX architecture}{9:9:0}
         The synthesizable VHDL description of the MWMR component corresponding to the
@@ -68 +70 @@
         The SystemC simulation module of the MWMR component with an AVALON bus interface plus
         the SystemC modules of the components of the ALTERA architectural template
-        not available in the SocLib component library.
+        currently not available in the SocLib component library.
     \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{0:0:0}
         The synthesizable VHDL description of the MWMR component corresponding to the
@@ -86 +88 @@
     system and the development of drivers for the hardware architectural templates
     and enhanced communication schemes defined in \novers{\specCsgManual} delivrable.
-    For the ALTERA and XILINX architectural template, the OSs must also be ported on
+    For the ALTERA and XILINX architectural templates, the OSs must also be ported on
     the NIOS2 and MICROBLAZE processors.
     \begin{livrable}
     \itemV{6}{8}{x}{\Supmc}{MUTEK OS}
-        The drivers required for the first CSG milestone (delivrable \csgCoachArch).
+        The drivers %FIXME = {???}
+        required for the first CSG milestone (delivrable \csgCoachArch).
     \itemV{8}{18}{x}{\Supmc}{MUTEK 0S}
         The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
@@ -96 +99 @@
         Maintenance work.
     \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0}
-        Port of MUTEK OS on the NIOS2 and MICROBLAZE processors.
+        Porting of MUTEK OS on the NIOS2 and MICROBLAZE processors.
     \itemV{6}{8}{x}{\Stima}{DNA OS}
         The drivers required for the first CSG milestone (delivrable \csgCoachArch).
@@ -104 +107 @@
         Maintenance work.
     \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{3:1:0}
-        Port of DNA OS on the NIOS2 and MICROBLAZE processors.
+        Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
     \end{livrable}
 \end{workpackage}