Changeset 111 for anr/task-4.tex


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Timestamp:
Feb 8, 2010, 12:22:11 PM (14 years ago)
Author:
coach
Message:

pc

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1 edited

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  • anr/task-4.tex

    r110 r111  
    5656    \begin{livrable}
    5757    \itemL{18}{24}{x}{\Stima}{UGH enhancement 1}{0:9:0}
    58         The UGH software whith support for treating automatically data dominated sections
     58        Release of the UGH software with support for treating automatically data dominated sections
    5959        included into a control dominated application.
    6060    \itemL{21}{27}{x}{\Stima}{UGH enhancement 2}{0:3:6}
    61         The UGH software that is able to generate a micro-architecture without the
     61        Release of the UGH software able to generate a micro-architecture without the
    6262        variable binding currently done by the designer.
    6363    \itemL{6}{18}{x}{\Subs}{GAUT enhancement 1}{0:0:0}
     
    7878        Release of the GAUT software that supports the features defined in \ST ????.
    7979    \end{livrable}
    80 \item In FPGA-SoC, the frequency is given by the processors and the BUS. The coprocessors
     80\item In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
    8181    generated by HLS synthesis must respect this frequency. However, the HLS tools can not
    8282    guarantee that the micro-architectures they generate accurately respect this
    8383    frequency. This is especially the case when the target is a FPGA device, because the
    8484    delays are really known only after the RTL synthesis and that estimated delays used
    85     by the HLS are very imprecize. The goal of this \ST is to provide a tool to adapt
     85    by the HLS are very inaccurate. The goal of this \ST is to provide a tool that adapts
    8686    the coprocessors frequency to the FPGA-SoC frequency after the coprocessor RTL
    8787    synthesis.
     
    9393    \itemL{24}{33}{x}{\Supmc}{frequency calibration}{2:.5:3.5}
    9494        The frequency calibration software consists of a driver in the FPGA-SoC operating
    95         system and of a control software on a PC.
     95        system and of a control software on a PC. %FIXME == {Pas clair pour le HPC. Comprends pas}
    9696    \end{livrable}
    9797\end{workpackage}
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