Changeset 123 for anr/task-6.tex


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Timestamp:
Feb 10, 2010, 1:59:01 AM (14 years ago)
Author:
coach
Message:

IA: 1) enter thales + zied 2) m.a.p

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1 edited

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  • anr/task-6.tex

    r114 r123  
    1414%
    1515\begin{workpackage}
    16   \item This \ST relies to the COACH use by \bull.
     16  \subtask This \ST relies to the COACH use by \bull.
    1717    \mustbecompleted{FIXME:BULL ajouter quelques lignes pour donner
    1818    1) type d'application (HPC ou embedded system, HLS),
    … …  
    3030        describing the result of the experimentations.
    3131    \end{livrable}
    32   \item This \ST relies to the COACH use by \navtel.
     32
     33  \subtask The objective of this sub-task is to specify the application and to develop the
     34    high level code. The application is in the domain of surveillance of critical
     35    infrastructures.
     36    The objective is to detect and classify the presence of humans in the restricted area.
     37    The algorithm is based on the work of Viola and Jones\cite{thales-viola}.
     38    It implements in particular a cascade of classifiers operating on Haar like features,
     39    where simple weak classifiers at the beginning of the cascade reject a majority of
     40    void sub-windows, before more complex classifiers concentrate on potential regions of
     41    interest.
     42    This application is computation intensive and also makes an intensive use of binary
     43    decision trees to cascade the filters, which makes it a good candidate to assess the
     44    association of CAL with parallelizing tools.\\
     45    Moreover, the higher levels of computing can involve tracking and data fusion between
     46    several camera streams and some other informations.
     47    The targeted system will be composed of one camera connected to a PC.
     48    All the computing part of the application is executed on a FPGA board connected to the
     49    PC.
     50    \begin{livrable}
     51      \itemV{0}{6}{d}{\Sthales}{\thales demonstrator (step 1)}
     52        \setMacroInAuxFile{trtAppSpecification}
     53        This delivrable is a document that specifies the application.
     54      \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{6:0:0}
     55        This delivrable is the code of the application spcecified former
     56        delivrable (\trtAppSpecification).
     57    \end{livrable}
     58
     59  \subtask \TRT will use its internal software environment tool SPEAR DE to describe the
     60    application. The tool is able to partition and to generate the code for the target. \\
     61    In this task, we will adapt SPEAR DE to generate the application description input of
     62    COACH framework. We will also describe the three templates of architecture in order to
     63    be able to partition the application on the architecture.
     64    \begin{livrable}
     65      \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:6:0}
     66        \setMacroInAuxFile{trtSpearde}
     67        Adaptation of SPEAR-DE for COACH framework.
     68    \end{livrable}
     69
     70  \subtask
     71    abbbaaa
     72    \begin{livrable}
     73      \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:6:0}
     74        \setMacroInAuxFile{trtSpearde}
     75        bbbb Adaptation of SPEAR-DE for COACH framework.
     76    \end{livrable}
     77
     78  \subtask
     79    In this task, \TRT will evaluate the COACH platform. In particular, \TRT will verify
     80    its ability to generate a whole VHDL of an embedded system on FPGA for an application
     81    mixing control and data flow aspects. \TRT will evaluate the performance of the
     82    generated system in terms of GOPS, and the design time from a high level description.
     83    \begin{livrable}
     84      \itemV{18}{24}{d+x}{\Sthales}{\thales demonstrator (step 2)}
     85        This delivrable is a document describing the result got for the application
     86        (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+18.
     87        The updated code of the application will be also provide.
     88      \itemV{24}{30}{d+x}{\Sthales}{\thales demonstrator (step 2)}
     89        This delivrable is a document describing the result got for the application
     90        (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+24.
     91        The updated code of the application will be also provide.
     92      \itemL{30}{36}{d+x}{\Sthales}{\thales demonstrator (step 2)}{0:6:6}
     93        This delivrable is a document that validates and evaluates COACH (final release)
     94        for the \thales demonstrators (\trtAppSpecification).
     95        The updated code of the application will be also provide.
     96    \end{livrable}
     97
     98  \subtask FLEXRAS proposes a SoC architecture integrating an embedded FPGA (eFPGA).
     99    The architecture is composed essentially of a processor, a bus and several RAMs.
     100    The embedded FPGA is connected to the bus and communicates with the other components.
     101    The (eFPGA) works in 2 modes:
     102    \begin{description}
     103      \item[Slave mode]
     104        As a DMA, the processor will send the configuration bitstream
     105        stored on the RAM to the eFPGA. In this mode, the eFPGA is considered as a
     106        writeable memory and is configured by the processor.
     107      \item[Master mode]
     108        Once the FPGA is programmed, it becomes a coprocessor achieving the aimed task.
     109    \end{description}
     110      The top architecture of this SoC based-platform will be generated using COACH
     111      framework. The application that will be run on the SoC corresponds initially to a
     112      graph of software tasks. Critical tasks will be identified and transformed
     113      automatically to hardware tasks using COACH high level synthesis feature. While
     114      software tasks will be run on the processor, hardware ones will be mapped on eFPGA
     115      to take advantage of its optimized resources and parallelism. FLEXRAS provides all
     116      the flow from RTL synthesis to bitstream generation.
     117    \begin{livrable}
     118      \itemL{0}{6}{d}{\Szied}{\zied architecture}{2.4:0:0}
     119        FLEXRAS will use IPs provided by LIP6 (vhdl models of SoCLIB) and its eFPGA IP to
     120        generate the SoC architecture.
     121        This delivrable is a document that describes this architecture.
     122      \itemL{6}{12}{h}{\Szied}{eFPGA/VCI component}{3.6:0:0}
     123        FLEXRAS has to adapt the eFPGA interface to connect it to the VCI bus.
     124        This delivrable is a VHDL description.
     125      \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0}
     126        Port of the bitstream loader to the MUTEK operating system.
     127      \itemL{18}{24}{x}{\Szied}{????????????}{0:2.4:0}
     128        \mustbecompleted{FIXME:PAS-CLAIR}
     129        FLEXRAS will propose a graph of software tasks. The hardware task to be mapped on
     130        the FPGA will be generated using the high level synthesis tool of COACH framework.
     131      \itemL{24}{30}{x}{\Szied}{eFPGA characterisation}{0:0:2.4}
     132        This delivrable is a file under the format defined by the delivrable
     133        \specMacroCell that characterizes the eFPGA. This will allows the COACH HLS tools
     134        to run taking into account the eFPGA delays.
     135      \itemL{30}{36}{d}{\Szied}{\zied evaluation}{0:0:3.6}
     136        This delivrable is a document that describes the tests, the validation and the
     137        evaluation of COACH with the \zied architecture and tools.
     138    \end{livrable}
     139
     140  \subtask This \ST relies to the COACH use by \navtel.
    33141    \\\mustbecompleted{FIXME:NAVTEL:BEGIN ---------------}\\
    34142    INDIQUER en quelques lignes \\
    … …  
    66174    \end{livrable}
    67175\end{workpackage}
    68 
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