Changeset 123

Timestamp:

Feb 10, 2010, 1:59:01 AM (15 years ago)

Author:

coach

Message:

IA: 1) enter thales + zied 2) m.a.p

Location:

anr

Files:

• Makefile (modified) (1 diff)
• anr.bib (modified) (3 diffs)
• anr.sty (modified) (2 diffs)
• anr.tex (modified) (3 diffs)
• gantt.l (modified) (1 diff)
• section-6.1.tex (modified) (3 diffs)
• section-7.tex (modified) (3 diffs)
• task-0.tex (modified) (3 diffs)
• task-1.tex (modified) (6 diffs)
• task-2.tex (modified) (3 diffs)
• task-3.tex (modified) (4 diffs)
• task-4.tex (modified) (4 diffs)
• task-5.tex (modified) (5 diffs)
• task-6.tex (modified) (3 diffs)
• task-7.tex (modified) (2 diffs)

anr/Makefile

@@ -17 +17 @@
                 table_ubs_full.tex table_ubs_short.tex \
                 table_xilinx_full.tex table_xilinx_short.tex \
+                table_inria_cairn_full.tex table_inria_cairn_short.tex \
 
 # PROGRAMS

anr/anr.bib

@@ -496 +496 @@
   publisher = {ACM}
 }
-
-
 
 %%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
@@ -583 +581 @@
 }
 
-
 @inproceedings{roma,
  author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
@@ -595 +592 @@
  }
 
-% 
+%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
+
+@inproceedings{thales-viola,
+ author = {Viola, Jones},
+ title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
+ booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
+ year = {2001},
+}

anr/anr.sty

@@ -87 +87 @@
  \def\taskname{T\the\taskcnt}%
  \begin{description}%
- \let\itemsave\item%
- \def\item{%
+ %\let\itemsave\item%
+ \def\subtask{%
     \global\advance\subtaskcnt1
     \def\subtaskname{S\taskname-\the\subtaskcnt}%
-    \itemsave[\subtaskname]}}
+    \item[\subtaskname]}}
 {\end{description}}
 
@@ -131 +131 @@
  }
  \livrablecnt-1
- \ifvmode\else\vspace{.75ex}\\\fi
+ \ifvmode \else\par\fi
     
  \def\itemV##1##2##3##4##5{%

anr/anr.tex

@@ -56 +56 @@
 \def\xilinx{XILINX\xspace}        \def\Sxilinx{\Sformat{XILX}\xspace}
 \def\bull{BULL\xspace}            \def\Sbull{\Sformat{BULL}\xspace}
-\def\thales{THALES\xspace}        \def\Sthales{\Sformat{THAL}\xspace}
+\def\thales{THALES\xspace}        \def\Sthales{\Sformat{TRT}\xspace} \let\TRT\thales
 \def\zied{FLEXRAS\xspace}         \def\Szied{\Sformat{FLEX}\xspace}
 \def\navtel{NAVTEL-SYSTEM\xspace} \def\Snavtel{\Sformat{NAV}\xspace}
@@ -126 +126 @@
 \end{tabular}\vspace{.5ex}\\
 \begin{tabular}{|c|c|c|c|}\hline
-  \begin{minipage}{4cm}\vspace*{.7ex}\mbox{}\\
-    Total requested funding
-  \vspace*{-.5ex}\\\end{minipage}
+  \begin{minipage}{4cm}\center
+    \vspace*{0.5ex}Total requested \\ funding
+  \end{minipage}
     & \makebox[3cm]{\mustbecompleted{XXXX} \euro}
       & \begin{minipage}{4.15cm}\center Project Duration \end{minipage}
@@ -380 +380 @@
 \bibliographystyle{plain}
 \bibliography{anr}
-\newpage
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

anr/gantt.l

@@ -623 +623 @@
         return;
     }
-    fprintf(curr->os,"\\begin{tabular}{|c|p{3.5cm}||r|r|r||r|}\\hline\n");
+    fprintf(curr->os,"\\begin{tabular}{|c|l||r|r|r||r|}\\hline\n");
     fprintf(curr->os,
         "number & \\multicolumn{1}{c||}{title} & \\multicolumn{3}{c||}{years } & total \\\\\\cline{3-5}\n");

anr/section-6.1.tex

@@ -109 +109 @@
 IST/AETHER ...). These projects are conducted through tight cooperation 
 with national and international companies and organizations (e.g. France 
-Telecom CNET, MATRA, CEA, ASTRIUM, THALES Com., THALES Avionics, AIRBUS, 
+Telecom CNET, MATRA, CEA, ASTRIUM, \thales Com., \thales Avionics, AIRBUS, 
 BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former 
 projects are for example the high-level synthesis tool GAUT, the UHLS 
@@ -154 +154 @@
 Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
 (following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies 
-(including FLEXRAS) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.
+(including \zied) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -213 +213 @@
 \subsubsection{\thales}
 
+\thales is a world leader for mission critical information systems, with activities in 3
+core businesses: aerospace (with all major aircraft manufacturers as customers), defence,
+and security (including ground transportation solutions). It employs 68000 people
+worldwide, and is present in 50 countries.  \thales develops its strategic capabilities in
+component, software and system engineering and architectures through its R \& T organization.
+Its six Divisions manage their strategy and technical co-ordination per domain with
+hundreds of Units in these Divisions developing their technical activities in close
+relationship with their market. In this environment, \thales Research \& Technology
+operates at the corporate level as the technical community network architect, in charge of
+developing upstream and \thales-wide R \& T activities, with vision and visibility.
+In support of \thales applications, TRT's mission is also to anticipate and speed up
+technology transfer from research to development in Divisions by developing collaborations
+in R\&T.
+
+Thales is international, but Europe-centered. Research \& Development activities are
+disseminated, and corporate Research and Technology is concentrated in Centres in France,
+the United Kingdom and the Netherlands.
+The R\&T in Thales emphasizes more particularly on critical information systems,
+processing, control and cognitive systems, and autonomous systems.
+
+A key mission of our R\&T centres is to have a bi-directional transfer, or “impedance
+matching” function between the scientific research network and the corresponding
+businesses. Benefiting from its presence and visibility on the international scene in
+advanced sciences, technology and software, \thales Research \& Technology is perceived as
+a valuable partner of the best research centres (academic or industrial) through
+recognized scientists and research engineer participation in collaborative projects.
+The TRT’s Information Science and Technology Group is able to develop innovative solutions
+along the information chain exploiting sensors data, through expertise in: computational
+architectures in embedded systems, typically suitable for autonomous system environments,
+mathematics and technologies for decision involving information fusion and cognitive
+processing, and cooperative technologies including man system interaction.
+The Embedded System Laboratory (ESL) of TRT involved in the COACH project is part of the
+Information Science and Technology Group.
+
+Like other labs of TRT, ESL is in charge of making the link between the needs from Thales
+business units and the emerging technologies, in particular through assessment and
+de-risking studies.
+It has a long experience on parallel architectures design, in particular on SIMD
+architectures used for image processing and signal processing applications and on
+reconfigurable architectures.
+ESL is also strongly involved in studies on programming tools for these types of
+architectures and has developed the SpearDE tool used in this project.
+The laboratory had coordinated the FP6 IST MORPHEUS project on reconfigurable technology,
+being highly involved in the associated programming toolset.
+
+The team is also involved in
+the FP6 IST FET AETHER project on self-adaptability technologies and coordinates national
+projects on MPSoC architecture and tools like the \verb+Ter@ops+ project (P\^{o}le de
+Comp\'{e}titivit\'{e} \verb+System@tic+) dedicated to the design of a MPSoC for intensive
+computing embedded systems.
+
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsubsection{\zied}
+
+\zied is an innovative start-up specialized in the conception of configurable circuits
+and the development of CAD tools. \zied provides a complete front-to-back-end generator
+of "hardware" reprogrammable IP cores that can be embedded in ASIC and ASSP SoC designs.
+\zied solution is based on a patented FPGA architecture delivering an unprecedented
+level of logic density. This high capacity is accessible using a traditional RTL flow from
+Verilog/VHDL synthesis all the way to bitstream generation.
+
+\zied is a spin-off from LIP6 (Laboratoire Informatique Paris 6) and was awarded at the
+French National Competition for Business Startup and Innovative Technology in 2007 and
+2009 in “emergence” and “creation” categories respectively.
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

anr/section-7.tex

@@ -1 @@
-\def\resstablestyletitle#1{\begin{tiny}\textbf{\textit{#1}}\end{tiny}}
+\def\resstablestyletitle#1{\begin{small}{\textit{#1}}\end{small}}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -40 +40 @@
 \subsection{Partner 2: \lip}
 
-%\ressourcehelp
 \begin{figure}\leavevmode\center
 \input{table_lip_full.tex}
 \caption{\label{ress-detail-lip}Man power in $mm$ for the delivrables of \lip.}
 \end{figure}
+
 \begin{description}
 \item [Equipment]
@@ -236 +236 @@
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{Partner 8: \thales}
-\ressourcehelp
+
+\begin{description}
+\item[Equipment]
+    In order to validate the design flow,TRT will buy FPGA developpement boards. The cost
+    for these FPGA boards is estimated to 20 k€ (6\% of the total ANR funding).
+\item[Personnel costs]
+    \mustbecompleted{
+    The effort to adapt SPEAR DE to generator the input files to COACH framework is
+    estimated to 22 man.month (6 in task 6 and 16 in task 7).
+    The effort to describe and develop the application is estimated to 12 man.month.
+    Finally we need 2 man.month for the partiticipation to the global specification in task 2.
+    }
+    \begin{center}\input{table_thales_full.tex}\end{center}
+\item[Subcontracting]
+    No subcontracting costs.
+\item[Travel]
+    The travel costs are associated to meeting, plenaries as well as participation to
+    conferences. The travel costs are estimated to 10k€. The travel costs are estimated to
+    5\% of the total requested ANR funding.
+\item[Expenses for inward billing] none
+\item[Other working costs] none
+\end{description}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
 \subsection{Partner 9: \zied}
-\ressourcehelp
+
+  \begin{center}\input{table_zied_full.tex}\end{center}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

anr/task-0.tex

@@ -20 +20 @@
 %
 \begin{workpackage}
-  \item This \ST consists in writing and ratifying the consortium agreement. 
+  \subtask This \ST consists in writing and ratifying the consortium agreement. 
     \begin{livrable}
     \itemL{0}{6}{d}{\Supmc}{Consortium agreement}{1:0:0}
         A document describing the consortium agreement, signed by all the partners.
     \end{livrable}
-  \item This \ST concerns the global management of the deliverables and of the global
+  \subtask This \ST concerns the global management of the deliverables and of the global
     organization of the project at all the levels.
     \begin{livrable}
@@ -33 +33 @@
         organization, the writting of the 3 review reports.
     \end{livrable}
-  \item This \ST consists managing the project at the partner level.
+  \subtask This \ST consists managing the project at the partner level.
     It includes mainly the progress monitoring, the record keeping the participation to the
     project meetings and the communication with the project leader and other partner.
@@ -39 +39 @@
       \itemL{0}{36}{}{\Supmc}{\upmc management}{1:1:1} Project management at the partner level.
     \end{livrable}
-  \item This \ST consists firstly in the building and maintenance of the 
+  \subtask This \ST consists firstly in the building and maintenance of the 
     development and dissemination infrastructure. It is also in charge of
     distributing the COACH releases.

anr/task-1.tex

@@ -12 +12 @@
 %
 \begin{workpackage}
-\item This \ST specifies the COACH environment for the system designer. At this
+\subtask This \ST specifies the COACH environment for the system designer. At this
     level the COACH framework is a black box. The deliverables are documents 
     specifying: how to feed COACH (the inputs), how to use COACH (the design flow),
@@ -49 +49 @@
             feed-backs of the demonstrator \STs.
     \end{livrable}
-\item This \ST specifies the software COACH structure. The deliverable is a
+\subtask This \ST specifies the software COACH structure. The deliverable is a
     document listing all the COACH software components and how they cooperate.
     \begin{livrable}
@@ -55 +55 @@
         It contains the software list and the data flow among them.
     \end{livrable}
-\item This \ST specifies the \xcoach format.
+\subtask This \ST specifies the \xcoach format.
     \begin{livrable}
     \itemV{0}{6}{d+x}{\Slip}{\xcoach format specification}
@@ -113 +113 @@
     \end{livrable}
     
-\item This \ST aims to define a tool in order to pilot the GCC/xcoach compiler.
+\subtask This \ST aims to define a tool in order to pilot the GCC/xcoach compiler.
 \mustbecompleted{FIXME: UBS :: Cette section et ses livrables doivent etre retouches}
     \begin{livrable}
@@ -122 +122 @@
     \end{livrable}
 
-\item Backend HLS tools use a characterized macro-cell library to build the
+\subtask Backend HLS tools use a characterized macro-cell library to build the
     micro-architecture of a coprocessor. The characterisation of a cell depends
     on the target device. The role of this \ST is to define the macro-cells and
@@ -129 +129 @@
     \begin{livrable}
     \itemL{0}{6}{d}{\Subs}{macro-cell definition}{0:0:0}
+        \setMacroInAuxFile{specMacroCell}
         The document defines the macro cell and the file format describing them.
     \itemL{6}{12}{x}{\Subs}{macro-cell library generator}{0:0:0}

anr/task-2.tex

@@ -29 +29 @@
 %
 \begin{workpackage}
-\item This \ST corresponds to the Coach System Generator (CSG) software.
+\subtask This \ST corresponds to the Coach System Generator (CSG) software.
     \begin{livrable}
     \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
@@ -46 +46 @@
         Maintenance work of CSG.
     \end{livrable}
-\item This \ST deals with the components of the architectural templates.
+\subtask This \ST deals with the components of the architectural templates.
     \\
     For the COACH architectural template, it consists of the devlopment of the VHDL
@@ -104 +104 @@
        listing that proposes VHDL generation enhancements.
     \end{livrable}
-\item This \ST consists of the configuration of the SocLib MUTEK and DNA operating
+\subtask This \ST consists of the configuration of the SocLib MUTEK and DNA operating
     system and the development of drivers for the hardware architectural templates
     and enhanced communication schemes defined in \novers{\specCsgManual} delivrable.

anr/task-3.tex

@@ -19 +19 @@
 %
 \begin{workpackage}
-  \item This sub-task aims at providing compiler support for custom instructions 
+  \subtask This sub-task aims at providing compiler support for custom instructions 
   within the HAS front-end. It will take as input the COACH intermediate 
   representation, and will output an annotated COACH IR containing the custom
   instructions definitions along with their occurrence in the application.
-
     \begin{livrable}
       \itemV{0}{18}{X}{\Sirisa}{ASIP compilation flow}
@@ -36 +35 @@
     \end{livrable}
  
- \item In this sub-task, we provide micro-architectural template models for the two target
+ \subtask In this sub-task, we provide micro-architectural template models for the two target
  processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow. 
  For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL) 
@@ -59 +58 @@
     \end{livrable}
 
-  \item Extraction of parallelism in polyhedral loops and conversion into a process network.
+  \subtask Extraction of parallelism in polyhedral loops and conversion into a process network.
 
    \begin{livrable}
@@ -85 +84 @@
 \end{workpackage}
    
-
-

anr/task-4.tex

@@ -31 +31 @@
 %FIXMA == {il faudrait fusionner les taches ST5-1 et ST5-2, non ???}
 \begin{workpackage}
-\item The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It
+\subtask The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It
     consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing
     them by \xcoach and \xcoachplus drivers i.e. C2X, X2SC and X2VHDL.
@@ -42 +42 @@
         Maintenance work of the UGH software.
     \end{livrable}
-\item The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It
+\subtask The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It
     consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing
     them by \xcoach and \xcoachplus drivers.
@@ -53 +53 @@
         Maintenance work of the GAUT software.
     \end{livrable}
-\item The goal of this \ST is to improve the UGH and GAUT HLS tools.
+\subtask The goal of this \ST is to improve the UGH and GAUT HLS tools.
     UGH and GAUT experimentations have shown respectively usefull enhancements.
     \begin{livrable}
@@ -79 +79 @@
         Release of the GAUT software that supports the features defined in \ST ????.
     \end{livrable}
-\item In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
+\subtask In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
     generated by HLS synthesis must respect this frequency. However, the HLS tools can not
     guarantee that the micro-architectures they generate accurately respect this

anr/task-5.tex

@@ -33 +33 @@
 \mustbecompleted { FIXME :: Ne doit onpas fusionner les taches ST6-1, ST6-2, ST6-3 et pourquoi pas ST6-4 ???}
 \begin{workpackage}
-\item This \ST is the definition of the communication schemes as a software API
+\subtask This \ST is the definition of the communication schemes as a software API
     (Application Programing Interface) between the application part running on the PC and
     the application part running on the FPGA-SoC.
@@ -41 +41 @@
         Specification describing the API.
     \end{livrable}
-\item This \ST consists in helping to partition applications.
+\subtask This \ST consists in helping to partition applications.
     It is a library implementing the communication API with features to profile
     the partitioned application.
@@ -51 +51 @@
         A library implementing the communication API defined in the {\hpcCommApi} delivrable.
     \end{livrable}
-\item This \ST deals with the implementation of the communication API on the both sides (PC
+\subtask This \ST deals with the implementation of the communication API on the both sides (PC
     part and FPGA-SoC).
     \begin{livrable}
@@ -65 +65 @@
         Maintenance work of HPC API for both Linux PC and MUTEK OS.
     \end{livrable}
-\item This \ST deals with the implementation of hardware and SystemC modules
+\subtask This \ST deals with the implementation of hardware and SystemC modules
     required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx.
     \begin{livrable}
@@ -79 +79 @@
     \end{livrable}
 
-\item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
+\subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
 It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
     \begin{livrable}

anr/task-6.tex

@@ -14 +14 @@
 %
 \begin{workpackage}
-  \item This \ST relies to the COACH use by \bull.
+  \subtask This \ST relies to the COACH use by \bull.
     \mustbecompleted{FIXME:BULL ajouter quelques lignes pour donner
     1) type d'application (HPC ou embedded system, HLS),
@@ -30 +30 @@
         describing the result of the experimentations.
     \end{livrable}
-  \item This \ST relies to the COACH use by \navtel.
+
+  \subtask The objective of this sub-task is to specify the application and to develop the
+    high level code. The application is in the domain of surveillance of critical
+    infrastructures.
+    The objective is to detect and classify the presence of humans in the restricted area.
+    The algorithm is based on the work of Viola and Jones\cite{thales-viola}.
+    It implements in particular a cascade of classifiers operating on Haar like features,
+    where simple weak classifiers at the beginning of the cascade reject a majority of
+    void sub-windows, before more complex classifiers concentrate on potential regions of
+    interest.
+    This application is computation intensive and also makes an intensive use of binary
+    decision trees to cascade the filters, which makes it a good candidate to assess the
+    association of CAL with parallelizing tools.\\
+    Moreover, the higher levels of computing can involve tracking and data fusion between
+    several camera streams and some other informations.
+    The targeted system will be composed of one camera connected to a PC.
+    All the computing part of the application is executed on a FPGA board connected to the
+    PC.
+    \begin{livrable}
+      \itemV{0}{6}{d}{\Sthales}{\thales demonstrator (step 1)}
+        \setMacroInAuxFile{trtAppSpecification}
+        This delivrable is a document that specifies the application.
+      \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{6:0:0}
+        This delivrable is the code of the application spcecified former
+        delivrable (\trtAppSpecification).
+    \end{livrable}
+
+  \subtask \TRT will use its internal software environment tool SPEAR DE to describe the
+    application. The tool is able to partition and to generate the code for the target. \\
+    In this task, we will adapt SPEAR DE to generate the application description input of
+    COACH framework. We will also describe the three templates of architecture in order to
+    be able to partition the application on the architecture.
+    \begin{livrable}
+      \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:6:0}
+        \setMacroInAuxFile{trtSpearde}
+        Adaptation of SPEAR-DE for COACH framework.
+    \end{livrable}
+
+  \subtask 
+    abbbaaa
+    \begin{livrable}
+      \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:6:0}
+        \setMacroInAuxFile{trtSpearde}
+        bbbb Adaptation of SPEAR-DE for COACH framework.
+    \end{livrable}
+
+  \subtask 
+    In this task, \TRT will evaluate the COACH platform. In particular, \TRT will verify
+    its ability to generate a whole VHDL of an embedded system on FPGA for an application
+    mixing control and data flow aspects. \TRT will evaluate the performance of the
+    generated system in terms of GOPS, and the design time from a high level description.
+    \begin{livrable}
+      \itemV{18}{24}{d+x}{\Sthales}{\thales demonstrator (step 2)}
+        This delivrable is a document describing the result got for the application
+        (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+18.
+        The updated code of the application will be also provide.
+      \itemV{24}{30}{d+x}{\Sthales}{\thales demonstrator (step 2)}
+        This delivrable is a document describing the result got for the application
+        (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+24.
+        The updated code of the application will be also provide.
+      \itemL{30}{36}{d+x}{\Sthales}{\thales demonstrator (step 2)}{0:6:6}
+        This delivrable is a document that validates and evaluates COACH (final release)
+        for the \thales demonstrators (\trtAppSpecification).
+        The updated code of the application will be also provide.
+    \end{livrable}
+
+  \subtask FLEXRAS proposes a SoC architecture integrating an embedded FPGA (eFPGA).
+    The architecture is composed essentially of a processor, a bus and several RAMs.
+    The embedded FPGA is connected to the bus and communicates with the other components.
+    The (eFPGA) works in 2 modes:
+    \begin{description}
+      \item[Slave mode]
+        As a DMA, the processor will send the configuration bitstream
+        stored on the RAM to the eFPGA. In this mode, the eFPGA is considered as a
+        writeable memory and is configured by the processor.
+      \item[Master mode]
+        Once the FPGA is programmed, it becomes a coprocessor achieving the aimed task.
+    \end{description}
+      The top architecture of this SoC based-platform will be generated using COACH
+      framework. The application that will be run on the SoC corresponds initially to a
+      graph of software tasks. Critical tasks will be identified and transformed
+      automatically to hardware tasks using COACH high level synthesis feature. While
+      software tasks will be run on the processor, hardware ones will be mapped on eFPGA
+      to take advantage of its optimized resources and parallelism. FLEXRAS provides all
+      the flow from RTL synthesis to bitstream generation.
+    \begin{livrable}
+      \itemL{0}{6}{d}{\Szied}{\zied architecture}{2.4:0:0}
+        FLEXRAS will use IPs provided by LIP6 (vhdl models of SoCLIB) and its eFPGA IP to
+        generate the SoC architecture.
+        This delivrable is a document that describes this architecture.
+      \itemL{6}{12}{h}{\Szied}{eFPGA/VCI component}{3.6:0:0}
+        FLEXRAS has to adapt the eFPGA interface to connect it to the VCI bus.
+        This delivrable is a VHDL description.
+      \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0}
+        Port of the bitstream loader to the MUTEK operating system.
+      \itemL{18}{24}{x}{\Szied}{????????????}{0:2.4:0}
+        \mustbecompleted{FIXME:PAS-CLAIR}
+        FLEXRAS will propose a graph of software tasks. The hardware task to be mapped on
+        the FPGA will be generated using the high level synthesis tool of COACH framework. 
+      \itemL{24}{30}{x}{\Szied}{eFPGA characterisation}{0:0:2.4}
+        This delivrable is a file under the format defined by the delivrable
+        \specMacroCell that characterizes the eFPGA. This will allows the COACH HLS tools
+        to run taking into account the eFPGA delays.
+      \itemL{30}{36}{d}{\Szied}{\zied evaluation}{0:0:3.6}
+        This delivrable is a document that describes the tests, the validation and the
+        evaluation of COACH with the \zied architecture and tools.
+    \end{livrable}
+
+  \subtask This \ST relies to the COACH use by \navtel.
     \\\mustbecompleted{FIXME:NAVTEL:BEGIN ---------------}\\
     INDIQUER en quelques lignes \\
@@ -66 +174 @@
     \end{livrable}
 \end{workpackage}
-

anr/task-7.tex

@@ -20 +20 @@
 %
 \begin{workpackage}
-  \item This \ST relies to the management of the WEB site and to the distribution of
+  \subtask This \ST relies to the management of the WEB site and to the distribution of
     the COACH releases.
     \begin{livrable}
@@ -38 +38 @@
       \CoutHorsD{6}{36}{\Stima}{dissemination}{0:2:2}
     \end{livrable}
-\item
+  \subtask
     \label{subtask-tutorial}
     This \ST consists of making a COACH tutorial and to publish it on the public WEB