Changeset 123


Ignore:
Timestamp:
Feb 10, 2010, 1:59:01 AM (15 years ago)
Author:
coach
Message:

IA: 1) enter thales + zied 2) m.a.p

Location:
anr
Files:
15 edited

Legend:

Unmodified
Added
Removed
  • anr/Makefile

    r99 r123  
    1717                table_ubs_full.tex table_ubs_short.tex \
    1818                table_xilinx_full.tex table_xilinx_short.tex \
     19                table_inria_cairn_full.tex table_inria_cairn_short.tex \
    1920
    2021# PROGRAMS
  • anr/anr.bib

    r120 r123  
    496496  publisher = {ACM}
    497497}
    498 
    499 
    500498
    501499%%%%%%%%%%%%% ASIP %%%%%%%%%%%%%%%%
     
    583581}
    584582
    585 
    586583@inproceedings{roma,
    587584 author = {Menard, Daniel and Casseau, Emmanuel and Khan, Shafqat and Sentieys, Olivier and Chevobbe, St\'{e}phane and Guyetant, St\'{e}phane and David, Raphael},
     
    595592 }
    596593
    597 %
     594%%%%%%%%%%%%% AUTRES %%%%%%%%%%%%%%%%
     595
     596@inproceedings{thales-viola,
     597 author = {Viola, Jones},
     598 title = {{Rapid Object Detection using a Boosted Cascade of Simple Feature}},
     599 booktitle = {Proceedings of Conference on Computer Vision and Pattern recognition},
     600 year = {2001},
     601}
  • anr/anr.sty

    r114 r123  
    8787 \def\taskname{T\the\taskcnt}%
    8888 \begin{description}%
    89  \let\itemsave\item%
    90  \def\item{%
     89 %\let\itemsave\item%
     90 \def\subtask{%
    9191    \global\advance\subtaskcnt1
    9292    \def\subtaskname{S\taskname-\the\subtaskcnt}%
    93     \itemsave[\subtaskname]}}
     93    \item[\subtaskname]}}
    9494{\end{description}}
    9595
     
    131131 }
    132132 \livrablecnt-1
    133  \ifvmode\else\vspace{.75ex}\\\fi
     133 \ifvmode \else\par\fi
    134134   
    135135 \def\itemV##1##2##3##4##5{%
  • anr/anr.tex

    r121 r123  
    5656\def\xilinx{XILINX\xspace}        \def\Sxilinx{\Sformat{XILX}\xspace}
    5757\def\bull{BULL\xspace}            \def\Sbull{\Sformat{BULL}\xspace}
    58 \def\thales{THALES\xspace}        \def\Sthales{\Sformat{THAL}\xspace}
     58\def\thales{THALES\xspace}        \def\Sthales{\Sformat{TRT}\xspace} \let\TRT\thales
    5959\def\zied{FLEXRAS\xspace}         \def\Szied{\Sformat{FLEX}\xspace}
    6060\def\navtel{NAVTEL-SYSTEM\xspace} \def\Snavtel{\Sformat{NAV}\xspace}
     
    126126\end{tabular}\vspace{.5ex}\\
    127127\begin{tabular}{|c|c|c|c|}\hline
    128   \begin{minipage}{4cm}\vspace*{.7ex}\mbox{}\\
    129     Total requested funding
    130   \vspace*{-.5ex}\\\end{minipage}
     128  \begin{minipage}{4cm}\center
     129    \vspace*{0.5ex}Total requested \\ funding
     130  \end{minipage}
    131131    & \makebox[3cm]{\mustbecompleted{XXXX} \euro}
    132132      & \begin{minipage}{4.15cm}\center Project Duration \end{minipage}
     
    380380\bibliographystyle{plain}
    381381\bibliography{anr}
    382 \newpage
    383382
    384383%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
  • anr/gantt.l

    r121 r123  
    623623        return;
    624624    }
    625     fprintf(curr->os,"\\begin{tabular}{|c|p{3.5cm}||r|r|r||r|}\\hline\n");
     625    fprintf(curr->os,"\\begin{tabular}{|c|l||r|r|r||r|}\\hline\n");
    626626    fprintf(curr->os,
    627627        "number & \\multicolumn{1}{c||}{title} & \\multicolumn{3}{c||}{years } & total \\\\\\cline{3-5}\n");
  • anr/section-6.1.tex

    r121 r123  
    109109IST/AETHER ...). These projects are conducted through tight cooperation
    110110with national and international companies and organizations (e.g. France
    111 Telecom CNET, MATRA, CEA, ASTRIUM, THALES Com., THALES Avionics, AIRBUS,
     111Telecom CNET, MATRA, CEA, ASTRIUM, \thales Com., \thales Avionics, AIRBUS,
    112112BarCo, STMicroelectronics, Alcatel-Lucent ...). Results of those or former
    113113projects are for example the high-level synthesis tool GAUT, the UHLS
     
    154154Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
    155155(following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies
    156 (including FLEXRAS) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.
     156(including \zied) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.
    157157
    158158%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     
    213213\subsubsection{\thales}
    214214
     215\thales is a world leader for mission critical information systems, with activities in 3
     216core businesses: aerospace (with all major aircraft manufacturers as customers), defence,
     217and security (including ground transportation solutions). It employs 68000 people
     218worldwide, and is present in 50 countries.  \thales develops its strategic capabilities in
     219component, software and system engineering and architectures through its R \& T organization.
     220Its six Divisions manage their strategy and technical co-ordination per domain with
     221hundreds of Units in these Divisions developing their technical activities in close
     222relationship with their market. In this environment, \thales Research \& Technology
     223operates at the corporate level as the technical community network architect, in charge of
     224developing upstream and \thales-wide R \& T activities, with vision and visibility.
     225In support of \thales applications, TRT's mission is also to anticipate and speed up
     226technology transfer from research to development in Divisions by developing collaborations
     227in R\&T.
     228
     229Thales is international, but Europe-centered. Research \& Development activities are
     230disseminated, and corporate Research and Technology is concentrated in Centres in France,
     231the United Kingdom and the Netherlands.
     232The R\&T in Thales emphasizes more particularly on critical information systems,
     233processing, control and cognitive systems, and autonomous systems.
     234
     235A key mission of our R\&T centres is to have a bi-directional transfer, or “impedance
     236matching” function between the scientific research network and the corresponding
     237businesses. Benefiting from its presence and visibility on the international scene in
     238advanced sciences, technology and software, \thales Research \& Technology is perceived as
     239a valuable partner of the best research centres (academic or industrial) through
     240recognized scientists and research engineer participation in collaborative projects.
     241The TRT’s Information Science and Technology Group is able to develop innovative solutions
     242along the information chain exploiting sensors data, through expertise in: computational
     243architectures in embedded systems, typically suitable for autonomous system environments,
     244mathematics and technologies for decision involving information fusion and cognitive
     245processing, and cooperative technologies including man system interaction.
     246The Embedded System Laboratory (ESL) of TRT involved in the COACH project is part of the
     247Information Science and Technology Group.
     248
     249Like other labs of TRT, ESL is in charge of making the link between the needs from Thales
     250business units and the emerging technologies, in particular through assessment and
     251de-risking studies.
     252It has a long experience on parallel architectures design, in particular on SIMD
     253architectures used for image processing and signal processing applications and on
     254reconfigurable architectures.
     255ESL is also strongly involved in studies on programming tools for these types of
     256architectures and has developed the SpearDE tool used in this project.
     257The laboratory had coordinated the FP6 IST MORPHEUS project on reconfigurable technology,
     258being highly involved in the associated programming toolset.
     259
     260The team is also involved in
     261the FP6 IST FET AETHER project on self-adaptability technologies and coordinates national
     262projects on MPSoC architecture and tools like the \verb+Ter@ops+ project (P\^{o}le de
     263Comp\'{e}titivit\'{e} \verb+System@tic+) dedicated to the design of a MPSoC for intensive
     264computing embedded systems.
     265
    215266%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    216267\subsubsection{\zied}
     268
     269\zied is an innovative start-up specialized in the conception of configurable circuits
     270and the development of CAD tools. \zied provides a complete front-to-back-end generator
     271of "hardware" reprogrammable IP cores that can be embedded in ASIC and ASSP SoC designs.
     272\zied solution is based on a patented FPGA architecture delivering an unprecedented
     273level of logic density. This high capacity is accessible using a traditional RTL flow from
     274Verilog/VHDL synthesis all the way to bitstream generation.
     275
     276\zied is a spin-off from LIP6 (Laboratoire Informatique Paris 6) and was awarded at the
     277French National Competition for Business Startup and Innovative Technology in 2007 and
     2782009 in “emergence” and “creation” categories respectively.
    217279
    218280%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
  • anr/section-7.tex

    r121 r123  
    1 \def\resstablestyletitle#1{\begin{tiny}\textbf{\textit{#1}}\end{tiny}}
     1\def\resstablestyletitle#1{\begin{small}{\textit{#1}}\end{small}}
    22
    33%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     
    4040\subsection{Partner 2: \lip}
    4141
    42 %\ressourcehelp
    4342\begin{figure}\leavevmode\center
    4443\input{table_lip_full.tex}
    4544\caption{\label{ress-detail-lip}Man power in $mm$ for the delivrables of \lip.}
    4645\end{figure}
     46
    4747\begin{description}
    4848\item [Equipment]
     
    236236%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    237237\subsection{Partner 8: \thales}
    238 \ressourcehelp
     238
     239\begin{description}
     240\item[Equipment]
     241    In order to validate the design flow,TRT will buy FPGA developpement boards. The cost
     242    for these FPGA boards is estimated to 20 k€ (6\% of the total ANR funding).
     243\item[Personnel costs]
     244    \mustbecompleted{
     245    The effort to adapt SPEAR DE to generator the input files to COACH framework is
     246    estimated to 22 man.month (6 in task 6 and 16 in task 7).
     247    The effort to describe and develop the application is estimated to 12 man.month.
     248    Finally we need 2 man.month for the partiticipation to the global specification in task 2.
     249    }
     250    \begin{center}\input{table_thales_full.tex}\end{center}
     251\item[Subcontracting]
     252    No subcontracting costs.
     253\item[Travel]
     254    The travel costs are associated to meeting, plenaries as well as participation to
     255    conferences. The travel costs are estimated to 10k€. The travel costs are estimated to
     256    5\% of the total requested ANR funding.
     257\item[Expenses for inward billing] none
     258\item[Other working costs] none
     259\end{description}
    239260
    240261%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    241262\subsection{Partner 9: \zied}
    242 \ressourcehelp
     263
     264  \begin{center}\input{table_zied_full.tex}\end{center}
    243265
    244266%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
  • anr/task-0.tex

    r106 r123  
    2020%
    2121\begin{workpackage}
    22   \item This \ST consists in writing and ratifying the consortium agreement.
     22  \subtask This \ST consists in writing and ratifying the consortium agreement.
    2323    \begin{livrable}
    2424    \itemL{0}{6}{d}{\Supmc}{Consortium agreement}{1:0:0}
    2525        A document describing the consortium agreement, signed by all the partners.
    2626    \end{livrable}
    27   \item This \ST concerns the global management of the deliverables and of the global
     27  \subtask This \ST concerns the global management of the deliverables and of the global
    2828    organization of the project at all the levels.
    2929    \begin{livrable}
     
    3333        organization, the writting of the 3 review reports.
    3434    \end{livrable}
    35   \item This \ST consists managing the project at the partner level.
     35  \subtask This \ST consists managing the project at the partner level.
    3636    It includes mainly the progress monitoring, the record keeping the participation to the
    3737    project meetings and the communication with the project leader and other partner.
     
    3939      \itemL{0}{36}{}{\Supmc}{\upmc management}{1:1:1} Project management at the partner level.
    4040    \end{livrable}
    41   \item This \ST consists firstly in the building and maintenance of the
     41  \subtask This \ST consists firstly in the building and maintenance of the
    4242    development and dissemination infrastructure. It is also in charge of
    4343    distributing the COACH releases.
  • anr/task-1.tex

    r115 r123  
    1212%
    1313\begin{workpackage}
    14 \item This \ST specifies the COACH environment for the system designer. At this
     14\subtask This \ST specifies the COACH environment for the system designer. At this
    1515    level the COACH framework is a black box. The deliverables are documents
    1616    specifying: how to feed COACH (the inputs), how to use COACH (the design flow),
     
    4949            feed-backs of the demonstrator \STs.
    5050    \end{livrable}
    51 \item This \ST specifies the software COACH structure. The deliverable is a
     51\subtask This \ST specifies the software COACH structure. The deliverable is a
    5252    document listing all the COACH software components and how they cooperate.
    5353    \begin{livrable}
     
    5555        It contains the software list and the data flow among them.
    5656    \end{livrable}
    57 \item This \ST specifies the \xcoach format.
     57\subtask This \ST specifies the \xcoach format.
    5858    \begin{livrable}
    5959    \itemV{0}{6}{d+x}{\Slip}{\xcoach format specification}
     
    113113    \end{livrable}
    114114   
    115 \item This \ST aims to define a tool in order to pilot the GCC/xcoach compiler.
     115\subtask This \ST aims to define a tool in order to pilot the GCC/xcoach compiler.
    116116\mustbecompleted{FIXME: UBS :: Cette section et ses livrables doivent etre retouches}
    117117    \begin{livrable}
     
    122122    \end{livrable}
    123123
    124 \item Backend HLS tools use a characterized macro-cell library to build the
     124\subtask Backend HLS tools use a characterized macro-cell library to build the
    125125    micro-architecture of a coprocessor. The characterisation of a cell depends
    126126    on the target device. The role of this \ST is to define the macro-cells and
     
    129129    \begin{livrable}
    130130    \itemL{0}{6}{d}{\Subs}{macro-cell definition}{0:0:0}
     131        \setMacroInAuxFile{specMacroCell}
    131132        The document defines the macro cell and the file format describing them.
    132133    \itemL{6}{12}{x}{\Subs}{macro-cell library generator}{0:0:0}
  • anr/task-2.tex

    r121 r123  
    2929%
    3030\begin{workpackage}
    31 \item This \ST corresponds to the Coach System Generator (CSG) software.
     31\subtask This \ST corresponds to the Coach System Generator (CSG) software.
    3232    \begin{livrable}
    3333    \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
     
    4646        Maintenance work of CSG.
    4747    \end{livrable}
    48 \item This \ST deals with the components of the architectural templates.
     48\subtask This \ST deals with the components of the architectural templates.
    4949    \\
    5050    For the COACH architectural template, it consists of the devlopment of the VHDL
     
    104104       listing that proposes VHDL generation enhancements.
    105105    \end{livrable}
    106 \item This \ST consists of the configuration of the SocLib MUTEK and DNA operating
     106\subtask This \ST consists of the configuration of the SocLib MUTEK and DNA operating
    107107    system and the development of drivers for the hardware architectural templates
    108108    and enhanced communication schemes defined in \novers{\specCsgManual} delivrable.
  • anr/task-3.tex

    r121 r123  
    1919%
    2020\begin{workpackage}
    21   \item This sub-task aims at providing compiler support for custom instructions
     21  \subtask This sub-task aims at providing compiler support for custom instructions
    2222  within the HAS front-end. It will take as input the COACH intermediate
    2323  representation, and will output an annotated COACH IR containing the custom
    2424  instructions definitions along with their occurrence in the application.
    25 
    2625    \begin{livrable}
    2726      \itemV{0}{18}{X}{\Sirisa}{ASIP compilation flow}
     
    3635    \end{livrable}
    3736 
    38  \item In this sub-task, we provide micro-architectural template models for the two target
     37 \subtask In this sub-task, we provide micro-architectural template models for the two target
    3938 processor architectures (NIOS-II and MIPS) supported within the COACH-ASIP design flow.
    4039 For each processor, we provide a simulation model (System-C) and a synthesizable model (VHDL)
     
    5958    \end{livrable}
    6059
    61   \item Extraction of parallelism in polyhedral loops and conversion into a process network.
     60  \subtask Extraction of parallelism in polyhedral loops and conversion into a process network.
    6261
    6362   \begin{livrable}
     
    8584\end{workpackage}
    8685   
    87 
    88 
  • anr/task-4.tex

    r113 r123  
    3131%FIXMA == {il faudrait fusionner les taches ST5-1 et ST5-2, non ???}
    3232\begin{workpackage}
    33 \item The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It
     33\subtask The goal of this \ST is to integrate the UGH HLS tool to the COACH framework. It
    3434    consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing
    3535    them by \xcoach and \xcoachplus drivers i.e. C2X, X2SC and X2VHDL.
     
    4242        Maintenance work of the UGH software.
    4343    \end{livrable}
    44 \item The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It
     44\subtask The goal of this \ST is to integrate the GAUT HLS tool to the COACH framework. It
    4545    consists of suppressing the C compiler and the SystemC and VHDL drivers and replacing
    4646    them by \xcoach and \xcoachplus drivers.
     
    5353        Maintenance work of the GAUT software.
    5454    \end{livrable}
    55 \item The goal of this \ST is to improve the UGH and GAUT HLS tools.
     55\subtask The goal of this \ST is to improve the UGH and GAUT HLS tools.
    5656    UGH and GAUT experimentations have shown respectively usefull enhancements.
    5757    \begin{livrable}
     
    7979        Release of the GAUT software that supports the features defined in \ST ????.
    8080    \end{livrable}
    81 \item In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
     81\subtask In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
    8282    generated by HLS synthesis must respect this frequency. However, the HLS tools can not
    8383    guarantee that the micro-architectures they generate accurately respect this
  • anr/task-5.tex

    r113 r123  
    3333\mustbecompleted { FIXME :: Ne doit onpas fusionner les taches ST6-1, ST6-2, ST6-3 et pourquoi pas ST6-4 ???}
    3434\begin{workpackage}
    35 \item This \ST is the definition of the communication schemes as a software API
     35\subtask This \ST is the definition of the communication schemes as a software API
    3636    (Application Programing Interface) between the application part running on the PC and
    3737    the application part running on the FPGA-SoC.
     
    4141        Specification describing the API.
    4242    \end{livrable}
    43 \item This \ST consists in helping to partition applications.
     43\subtask This \ST consists in helping to partition applications.
    4444    It is a library implementing the communication API with features to profile
    4545    the partitioned application.
     
    5151        A library implementing the communication API defined in the {\hpcCommApi} delivrable.
    5252    \end{livrable}
    53 \item This \ST deals with the implementation of the communication API on the both sides (PC
     53\subtask This \ST deals with the implementation of the communication API on the both sides (PC
    5454    part and FPGA-SoC).
    5555    \begin{livrable}
     
    6565        Maintenance work of HPC API for both Linux PC and MUTEK OS.
    6666    \end{livrable}
    67 \item This \ST deals with the implementation of hardware and SystemC modules
     67\subtask This \ST deals with the implementation of hardware and SystemC modules
    6868    required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx.
    6969    \begin{livrable}
     
    7979    \end{livrable}
    8080
    81 \item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
     81\subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
    8282It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
    8383    \begin{livrable}
  • anr/task-6.tex

    r114 r123  
    1414%
    1515\begin{workpackage}
    16   \item This \ST relies to the COACH use by \bull.
     16  \subtask This \ST relies to the COACH use by \bull.
    1717    \mustbecompleted{FIXME:BULL ajouter quelques lignes pour donner
    1818    1) type d'application (HPC ou embedded system, HLS),
     
    3030        describing the result of the experimentations.
    3131    \end{livrable}
    32   \item This \ST relies to the COACH use by \navtel.
     32
     33  \subtask The objective of this sub-task is to specify the application and to develop the
     34    high level code. The application is in the domain of surveillance of critical
     35    infrastructures.
     36    The objective is to detect and classify the presence of humans in the restricted area.
     37    The algorithm is based on the work of Viola and Jones\cite{thales-viola}.
     38    It implements in particular a cascade of classifiers operating on Haar like features,
     39    where simple weak classifiers at the beginning of the cascade reject a majority of
     40    void sub-windows, before more complex classifiers concentrate on potential regions of
     41    interest.
     42    This application is computation intensive and also makes an intensive use of binary
     43    decision trees to cascade the filters, which makes it a good candidate to assess the
     44    association of CAL with parallelizing tools.\\
     45    Moreover, the higher levels of computing can involve tracking and data fusion between
     46    several camera streams and some other informations.
     47    The targeted system will be composed of one camera connected to a PC.
     48    All the computing part of the application is executed on a FPGA board connected to the
     49    PC.
     50    \begin{livrable}
     51      \itemV{0}{6}{d}{\Sthales}{\thales demonstrator (step 1)}
     52        \setMacroInAuxFile{trtAppSpecification}
     53        This delivrable is a document that specifies the application.
     54      \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{6:0:0}
     55        This delivrable is the code of the application spcecified former
     56        delivrable (\trtAppSpecification).
     57    \end{livrable}
     58
     59  \subtask \TRT will use its internal software environment tool SPEAR DE to describe the
     60    application. The tool is able to partition and to generate the code for the target. \\
     61    In this task, we will adapt SPEAR DE to generate the application description input of
     62    COACH framework. We will also describe the three templates of architecture in order to
     63    be able to partition the application on the architecture.
     64    \begin{livrable}
     65      \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:6:0}
     66        \setMacroInAuxFile{trtSpearde}
     67        Adaptation of SPEAR-DE for COACH framework.
     68    \end{livrable}
     69
     70  \subtask
     71    abbbaaa
     72    \begin{livrable}
     73      \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:6:0}
     74        \setMacroInAuxFile{trtSpearde}
     75        bbbb Adaptation of SPEAR-DE for COACH framework.
     76    \end{livrable}
     77
     78  \subtask
     79    In this task, \TRT will evaluate the COACH platform. In particular, \TRT will verify
     80    its ability to generate a whole VHDL of an embedded system on FPGA for an application
     81    mixing control and data flow aspects. \TRT will evaluate the performance of the
     82    generated system in terms of GOPS, and the design time from a high level description.
     83    \begin{livrable}
     84      \itemV{18}{24}{d+x}{\Sthales}{\thales demonstrator (step 2)}
     85        This delivrable is a document describing the result got for the application
     86        (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+18.
     87        The updated code of the application will be also provide.
     88      \itemV{24}{30}{d+x}{\Sthales}{\thales demonstrator (step 2)}
     89        This delivrable is a document describing the result got for the application
     90        (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+24.
     91        The updated code of the application will be also provide.
     92      \itemL{30}{36}{d+x}{\Sthales}{\thales demonstrator (step 2)}{0:6:6}
     93        This delivrable is a document that validates and evaluates COACH (final release)
     94        for the \thales demonstrators (\trtAppSpecification).
     95        The updated code of the application will be also provide.
     96    \end{livrable}
     97
     98  \subtask FLEXRAS proposes a SoC architecture integrating an embedded FPGA (eFPGA).
     99    The architecture is composed essentially of a processor, a bus and several RAMs.
     100    The embedded FPGA is connected to the bus and communicates with the other components.
     101    The (eFPGA) works in 2 modes:
     102    \begin{description}
     103      \item[Slave mode]
     104        As a DMA, the processor will send the configuration bitstream
     105        stored on the RAM to the eFPGA. In this mode, the eFPGA is considered as a
     106        writeable memory and is configured by the processor.
     107      \item[Master mode]
     108        Once the FPGA is programmed, it becomes a coprocessor achieving the aimed task.
     109    \end{description}
     110      The top architecture of this SoC based-platform will be generated using COACH
     111      framework. The application that will be run on the SoC corresponds initially to a
     112      graph of software tasks. Critical tasks will be identified and transformed
     113      automatically to hardware tasks using COACH high level synthesis feature. While
     114      software tasks will be run on the processor, hardware ones will be mapped on eFPGA
     115      to take advantage of its optimized resources and parallelism. FLEXRAS provides all
     116      the flow from RTL synthesis to bitstream generation.
     117    \begin{livrable}
     118      \itemL{0}{6}{d}{\Szied}{\zied architecture}{2.4:0:0}
     119        FLEXRAS will use IPs provided by LIP6 (vhdl models of SoCLIB) and its eFPGA IP to
     120        generate the SoC architecture.
     121        This delivrable is a document that describes this architecture.
     122      \itemL{6}{12}{h}{\Szied}{eFPGA/VCI component}{3.6:0:0}
     123        FLEXRAS has to adapt the eFPGA interface to connect it to the VCI bus.
     124        This delivrable is a VHDL description.
     125      \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0}
     126        Port of the bitstream loader to the MUTEK operating system.
     127      \itemL{18}{24}{x}{\Szied}{????????????}{0:2.4:0}
     128        \mustbecompleted{FIXME:PAS-CLAIR}
     129        FLEXRAS will propose a graph of software tasks. The hardware task to be mapped on
     130        the FPGA will be generated using the high level synthesis tool of COACH framework.
     131      \itemL{24}{30}{x}{\Szied}{eFPGA characterisation}{0:0:2.4}
     132        This delivrable is a file under the format defined by the delivrable
     133        \specMacroCell that characterizes the eFPGA. This will allows the COACH HLS tools
     134        to run taking into account the eFPGA delays.
     135      \itemL{30}{36}{d}{\Szied}{\zied evaluation}{0:0:3.6}
     136        This delivrable is a document that describes the tests, the validation and the
     137        evaluation of COACH with the \zied architecture and tools.
     138    \end{livrable}
     139
     140  \subtask This \ST relies to the COACH use by \navtel.
    33141    \\\mustbecompleted{FIXME:NAVTEL:BEGIN ---------------}\\
    34142    INDIQUER en quelques lignes \\
     
    66174    \end{livrable}
    67175\end{workpackage}
    68 
  • anr/task-7.tex

    r113 r123  
    2020%
    2121\begin{workpackage}
    22   \item This \ST relies to the management of the WEB site and to the distribution of
     22  \subtask This \ST relies to the management of the WEB site and to the distribution of
    2323    the COACH releases.
    2424    \begin{livrable}
     
    3838      \CoutHorsD{6}{36}{\Stima}{dissemination}{0:2:2}
    3939    \end{livrable}
    40 \item
     40  \subtask
    4141    \label{subtask-tutorial}
    4242    This \ST consists of making a COACH tutorial and to publish it on the public WEB
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