Changeset 126


Ignore:
Timestamp:
Feb 10, 2010, 5:59:35 PM (14 years ago)
Author:
coach
Message:

OM modification pendant la réunion du 10 février

Location:
anr
Files:
14 edited

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  • anr/anr.tex

    r123 r126  
    103103Acronym of the proposal & COACH \\\hline
    104104Title of the proposal in French &
    105         \textbf{C}onception d'\textbf{A}rchitecture par
     105        \textbf{C}onception d'\textbf{A}rchitecture sur FPGA par
    106106        \textbf{C}ompilation et synt\textbf{H}\`{e}se\\\hline
    107107\begin{minipage}{\linewidth}Title of the proposal in\\ English\end{minipage}
    108         & \mustbecompleted{FIXME} \\\hline
    109 Theme \mustbecompleted{FIXME} & \setlength{\unitlength}{5.0mm}\begin{picture}(20,1)
     108        & ARchitecture DEsign on FPGA by COmpilation and synthesis \\\hline
     109Theme & \setlength{\unitlength}{5.0mm}\begin{picture}(20,1)
    110110        \put( 0.5,0){\framebox(0.6,0.6){X}} \put( 1.5,0){1}
    111         \put( 3.5,0){\framebox(0.6,0.6){X}} \put( 4.5,0){2}
    112         \put( 6.5,0){\framebox(0.6,0.6){X}} \put( 7.5,0){3}
     111        \put( 3.5,0){\framebox(0.6,0.6){/}} \put( 4.5,0){2}
     112        \put( 6.5,0){\framebox(0.6,0.6){/}} \put( 7.5,0){3}
    113113        \put( 9.5,0){\framebox(0.6,0.6){ }} \put(10.5,0){4}
    114114        \put(12.5,0){\framebox(0.6,0.6){ }} \put(13.5,0){5}

  • anr/section-4.1.tex

    r119 r126  
    6969simulator. Once the partitioning is validated, the design of the FPGA part
    7070is done through \verb!CSG! (figure~\ref{archi-csg}).
    71 \mustbecompleted{FIXME == MODIFICATION DE LA FIGURE}
    7271\parlf
    7372The project is split into 8 tasks numbered from 1 to 8. There are described

  • anr/section-4.2.tex

    r38 r126  
    11\begin{description}
    22\item[Project management structure]
    3 First of all, a good management requires that each task is assigned to a Task Leader.
     3Each task is assigned to a Task Leader.
    44The Task Leaders assist the project leader in the technical organization, effort
    5 management, of the co-operation and the reporting of the progress. Each month the Task
    6 Leaders have to send to the project leader short update report with the
    7 main high-lights, major opportunities and problems according to the work-plan.
     5management, of the co-operation and the reporting of the progress.
     6A steering committee is composed by task leaders and the project leader.
     7The steering committee has a monthly conference call and is in charge of conflict
     8management if necessary.
     9Each task leader has to report on the main high-lights, major
     10opportunities and problems according to the work-plan.
     11The redaction of the 6-month reports is the responsability of the steering committee.
    812Therefore, each Partner has the responsibility to monthly inform the task Leaders of the
    913current development of the \ST he has in charge.
    10 COACH will be organized in \mustbecompleted{FIXME: 8} tasks whose interactions are presented in
     14COACH will be organized in 8 tasks whose interactions are presented in
    1115Figure~\ref{dependence-task}.
    1216

  • anr/section-4.4.tex

    r113 r126  
    4747    supported.
    4848    The main restriction are:
    49     1) The HAS tools have not been yet enhanced,
     49    1) The backend HAS tools have not been yet enhanced,
    5050    2) dynamic partial reconfiguration is not supported,
    51     3) \mustbecompleted{FIXME:ALL .....}
     51    3)
     52        4)\mustbecompleted{FIXME:ALL .....}
    5253\item[Final Release ($T0+36$)]
    5354\end{description}
    … …  
    5758at the integration phase is significantly reduced.
    5859\par
    59 The project has several critical issues:
     60The risks that have been identified at the beginning of the project are the following:
    6061\begin{description}
    61 \item[\xcoachplus format (\novers{\specXcoachDoc}, \novers{\specXcoachToCA})]
    62     Because all the HAS tools rely on it, it is a
    63     crucial task. There are no work-arround but as mentionned in
    64     section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) we have worked on it
    65         for a year and are confident.
    66 \item[\xcoachplus format (\novers{\specXcoachDoc},
    67       \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
    68     Its aim is the generation of the coprocessors (hardware \& prototyping model).
    69     By centralizing the coprocessor generation, it guarantees their functioning
    70     independently of the used HAS tools.
    71         Our experience with UGH and GAUT give us confidence in the succes of this
    72         task.
    73 \item[prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC},
    74      {\csgXilinxSystemC}]
    75      The SocLib component library contains most of the SystemC models used for the
    76      prototyping description of the ALTERA and XILINX architectural templates.
    77      Nevertheless, at this time we do not know how many are missing and if the existing
    78      are really useables.
    79      If the work of theses tasks is too important, they will be abandoned.
    80      In this case the work-arround to prototype the XILINX and ALTERA architectural
    81      templates is to use the COACH one. These architectures being very similar, the
    82      simulation results must be proportional. Theses tasks will be changed by measuring
    83      the deviance.
     62\item[\xcoach format (\novers{\specXcoachDoc}, \novers{\specXcoachToCA})]
     63        Partners have to agree on a convenient exchange format for all tools involved.
     64        Because all the HAS tools rely on it, the \xcoach format specification is a
     65    crucial step. There are no work-arround but as mentionned in
     66    section~\ref{xcoach-problem} (page~\pageref{xcoach-problem}) the five academic partners have worked on it
     67        for a full year and a first document already exists.
     68%\item[\xcoachplus format (\novers{\specXcoachDoc},
     69%      \novers{\specXcoachToSystemC}, \novers{\specXcoachToVhdl})]
     70%    Its aim is the generation of the coprocessors (hardware \& prototyping model).
     71%    By centralizing the coprocessor generation, it guarantees their functioning
     72%    independently of the used HAS tools.
     73%       Our experience with UGH and GAUT give us confidence in the succes of this
     74%       task.
     75\item[Virtual prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC},
     76     {\csgXilinxSystemC})]
     77     The SocLib component library contains several SystemC models used for the virtual
     78     prototyping of the ALTERA and XILINX architectural templates (NIOS and Microblaze processor cores).
     79     Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped.
     80     If the workload of this simulation model development is too important, virtual prototyping
     81         of those architectural templates will not be directly supported.
     82         The three architectural templates being quite similar, the virtual
     83         prototyping will use the neutral architectural template.
    8484\item[VCI/AVALON \& VCI/PLB bridges (\novers{\hpcAvalonBridge}, \novers{\hpcPlbBridge})]
    8585     If one of these tasks is impossible or too important or leads to inefficiency,
    … …  
    8787     In this case, the COACH architectural template will not be available for HPC and
    8888     a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
    89      prototyping.
     89     virtual prototyping.
    9090\end{description}
    9191

  • anr/section-5.tex

    r119 r126  
    4242For commercial use, commercial licenses will be negociated between the owners and the customers.
    4343\item
    44 The proprietary ALTERA and XILINX IP core libraries are commercial products
     44The proprietary ALTERA, XILINX and FLEXRAS IP core libraries are commercial products
    4545that are not involved by the free software policy, but these libraries will be supported by the
    4646synthesis tools developped in the Coach project.

  • anr/section-7.tex

    r125 r126  
    223223    A permanent engineer will be assigned full time to the project for a duration of 20
    224224    months as shown in the table below:
    225     \begin{center}\input{table_bull_short.tex}\end{center}
     225    \begin{center}\input{table_bull_full.tex}\end{center}
    226226\item[Subcontracting]
    227227    No subcontracting costs.
    … …  
    242242    for these FPGA boards is estimated to 20 k\euro (6\% of the total ANR funding).
    243243\item[Personnel costs]
    244     \mustbecompleted{
    245244    The effort to adapt SPEAR DE to generator the input files to COACH framework is
    246     estimated to 22 man.month (6 in task 6 and 16 in task 7).
    247     The effort to describe and develop the application is estimated to 12 man.month.
    248     Finally we need 2 man.month for the partiticipation to the global specification in task 2.
    249     }
     245    estimated to 13 man.months.
     246    The effort to describe and develop the application is estimated to 14 man.month.
     247    Finally we need 1 man.month for the partiticipation to the global specification in task 2.
    250248    \begin{center}\input{table_thales_full.tex}\end{center}
    251249\item[Subcontracting]

  • anr/task-0.tex

    r123 r126  
    11\begin{taskinfo}
    22\let\UPMC\leader
    3 \let\ALL\disable
     3\let\ALL\enable
    44\end{taskinfo}
    55%
    66\begin{objectif}
    7 This task relies to the monitoring of the COACH project. Its main objectives are:
     7This task relates to the monitoring of the COACH project. Its main objectives are:
    88\begin{itemize}
    99\item To ensure the appropriate progress of the project,

  • anr/task-1.tex

    r123 r126  
    5252    document listing all the COACH software components and how they cooperate.
    5353    \begin{livrable}
     54      \CoutHorsD{0}{12}{\Sthales}{user specification}{1:0:0}
    5455    \itemL{0}{6}{d}{\Supmc}{decription of \ganttlf software architecture}{1:0:0}
    5556        It contains the software list and the data flow among them.

  • anr/task-2.tex

    r123 r126  
    1616\item the development of all the missing components (SytemC models and/or synthesizable VHDL models
    1717of the IP-cores),
    18 \item the configuration and the development of drivers \mustbecompleted{FIXME:: driver de quoi ???}
    19 of the operating systems,
    20 \item the CSG software that generates the SystemC simulators for prototyping and the synthesizable description
    21 of the FPGA-SoC system (i.e. its bitstream), \mustbecompleted{FIXME:: VHDL ou bitstream ???}
     18\item the configuration and the development of drivers of the operating systems (Board Support Package, HAL),
     19\item the CSG software that generates the SystemC simulators for prototyping and the FPGA-SoC system
     20including its bitstream and software executable code,
    2221\item the specification of enhanced communication schemes and their sofware and hardware implementations.
    2322\end{itemize}
    … …  
    3534        hardware architecture template.
    3635    \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
    37         This milestone adds to CSG the support to the XILINX and ALTERA architectural
    38         templates and to the enhanced communication system.
    39         In this milestone only the SystemC prototyping will be supported for the XILINX
    40         and ALTERA architectural template.
    41         HAS is available. \mustbecompleted{FIXME:: ca veut dire ???}
     36        The second release of CSG supports the XILINX and ALTERA architectural
     37        templates and the enhanced communication system, but only for SystemC prototyping.
     38        This release integrates a first integration of HLS tools.
    4239    \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
    4340        This milestone extends CSG (\csgPrototypingOnly) to
    4441        FPGA-SoC generation for the XILINX and ALTERA architectural template.
    4542    \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:6}
    46         Maintenance work of CSG.
     43        Final release of CSG.
    4744    \end{livrable}
    4845\subtask This \ST deals with the components of the architectural templates.
    4946    \\
    50     For the COACH architectural template, it consists of the devlopment of the VHDL
    51     synthesizable description of the missing components. \mustbecompleted{FIXME :: pas clair missing components}
     47    For the COACH architectural template, it consists of the development of the VHDL
     48    synthesizable description of the missing communication components (MWMR)
     49        in order to support the process network communication model.
    5250    Notice that the SystemC models
    5351    comes from the SocLib ANR project, the processor with its cache comes from the TSAR
    … …  
    5553    \\
    5654    For the XILINX and ALTERA architectural templates, we use the XILINX and ALTERA IPs (NIOS, Microblaze, memories, busses...).
    57     The missing component is the MWMR used for communication between the tasks of the
    58     application.
    5955    \begin{livrable}
    6056    \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0}
    … …  
    111107    \begin{livrable}
    112108    \itemV{6}{8}{x}{\Supmc}{MUTEK OS}
    113         The drivers \mustbecompleted{FIXME :: ???}
    114         required for the first CSG milestone (delivrable \csgCoachArch).
     109        The drivers required for the first CSG milestone (delivrable \csgCoachArch).
    115110    \itemV{8}{18}{x}{\Supmc}{MUTEK 0S}
    116111        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).

  • anr/task-3.tex

    r123 r126  
    22\let\LIP\leader
    33\let\IRISA\enable
     4\let\UBS\enable
     5\let\UPMC\enable
     6\let\TIMA\enable
    47\end{taskinfo}
    58%
    … …  
    1518as possible, identify communication channels, and output an \xcoach
    1619description.
    17 \mustbecompleted {FIXME :: Impossible d'utiliser les transformations de boucles pour amélierer la partie SW ??? }
    1820\end{objectif}
    1921%

  • anr/task-4.tex

    r123 r126  
    9595    \itemL{24}{33}{x}{\Supmc}{frequency calibration}{2:.5:3.5}
    9696        The frequency calibration software consists of a driver in the FPGA-SoC operating
    97         system and of a control software on a PC. \mustbecompleted {FIXME :: Pas clair pour le HPC. Comprends pas}
     97        system and of a control software.
    9898    \itemL{24}{27}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (5)}{0:0:1}
    9999       This deliverable consists in optimizing the VHDL description provided in

  • anr/task-5.tex

    r123 r126  
    33
    44\begin{taskinfo}
    5 \let\UPMC\leader
     5\let\BULL\leader
     6\let\UPMC\enable
    67\let\TIMA\enable
     8\let\THALES\enable
    79\let\XILINX\enable
    810\end{taskinfo}
    … …  
    1416\item Providing a software tool that helps the HPC designer to find a good partition of the initial application
    1517    (figure~\ref{archi-hpc}).
    16 \item Providing communication schemes between the software part running on the PC and the
    17 FPGA-SoC. \mustbecompleted{ FIXME :: Quelle difference avec l'item qui suit ???}
     18\item specification of the communication schemes between the software part running on the PC and the
     19FPGA-SoC.
    1820\item Implementing the communication scheme at all levels: partition help, software
    1921implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
    … …  
    2527transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for
    2628their FPGA and that GPU HPC softwares use also it.
    27 \mustbecompleted { FIXME :: ai supprime (mis en commentaire) la phrse qui suivait}
    2829%This will allow us at least to be inspired by GPU communication schemes and may be to reuse
    2930%parts of the GPU softwares.
    … …  
    3738    the application part running on the FPGA-SoC.
    3839    \begin{livrable}
    39     \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0}
     40    \itemL{0}{6}{d}{\Sbull}{HPC communication API}{1.0:0:0}
    4041        \setMacroInAuxFile{hpcCommApi}
    4142        Specification describing the API.

  • anr/task-6.tex

    r125 r126  
    11\begin{taskinfo}
    2 \let\IRISA\leader
     2\let\IRISA\enable
    33\let\BULL\enable
    4 \let\THALES\enable
     4\let\THALES\leader
    55\let\NAVTEL\enable
    66\let\ZIED\enable
    … …  
    2626        The deliverable is the specification of the demonstrator in COACH input format
    2727        defined in the {\specGenManual} deliverable.
    28       \itemL{12}{36}{d}{\Sbull}{\bull demonstrator}{9:6:5}
     28      \itemL{12}{36}{d}{\Sbull}{\bull demonstrator}{9:5:5}
    2929        Validation of the demonstrator, the deliverable is a document
    3030        describing the result of the experimentations.
    … …  
    5252        \setMacroInAuxFile{trtAppSpecification}
    5353        This delivrable is a document that specifies the application.
    54       \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{6:0:0}
     54      \itemL{6}{12}{x}{\Sthales}{\thales demonstrator (step 1)}{4:0:0}
    5555        This delivrable is the code of the application spcecified former
    5656        delivrable (\trtAppSpecification).
    … …  
    6363    be able to partition the application on the architecture.
    6464    \begin{livrable}
    65       \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:6:0}
     65      \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:7:0}
    6666        \setMacroInAuxFile{trtSpearde}
    6767        Adaptation of SPEAR-DE for COACH framework.
    68     \end{livrable}
    69 
    70   \subtask
    71     abbbaaa
    72     \begin{livrable}
    73       \itemL{6}{18}{x}{\Sthales}{SPEAR-DE adaptation}{6:6:0}
    74         \setMacroInAuxFile{trtSpearde}
    75         bbbb Adaptation of SPEAR-DE for COACH framework.
    7668    \end{livrable}
    7769
    … …  
    9082        (\trtAppSpecification) with SPEAR-DE (\trtSpearde) using COACH milestone of T0+24.
    9183        The updated code of the application will be also provide.
    92       \itemL{30}{36}{d+x}{\Sthales}{\thales demonstrator (step 2)}{0:6:6}
     84      \itemL{30}{36}{d+x}{\Sthales}{\thales demonstrator (step 2)}{0:5:5}
    9385        This delivrable is a document that validates and evaluates COACH (final release)
    9486        for the \thales demonstrators (\trtAppSpecification).

  • anr/task-7.tex

    r123 r126  
    11\begin{taskinfo}
    22\let\UPMC\leader
    3 \let\XILINX\enable
     3\let\ALL\enable
    44\end{taskinfo}
    55%
    … …  
    4343    site. The tutorial example will also be used as reference demonstrator of the
    4444    framework.
    45     The application of this tutorial can be a Motion JPEG application, or an application
    46     that draws in 3D (under open GL) a simulation of a meteor cloud attracted by a sun and
    47     planets, or a database management system.
     45    The application of this tutorial will be a Motion JPEG application.
    4846  \begin{livrable}
    4947    \itemV{0}{6}{x}{\Supmc}{tutorial specification}
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