Changeset 126 for anr/task-5.tex
- Timestamp:
- Feb 10, 2010, 5:59:35 PM (14 years ago)
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anr/task-5.tex
r123 r126 3 3 4 4 \begin{taskinfo} 5 \let\UPMC\leader 5 \let\BULL\leader 6 \let\UPMC\enable 6 7 \let\TIMA\enable 8 \let\THALES\enable 7 9 \let\XILINX\enable 8 10 \end{taskinfo} … … 14 16 \item Providing a software tool that helps the HPC designer to find a good partition of the initial application 15 17 (figure~\ref{archi-hpc}). 16 \item Providingcommunication schemes between the software part running on the PC and the17 FPGA-SoC. \mustbecompleted{ FIXME :: Quelle difference avec l'item qui suit ???}18 \item specification of the communication schemes between the software part running on the PC and the 19 FPGA-SoC. 18 20 \item Implementing the communication scheme at all levels: partition help, software 19 21 implementation both on the PC and in the operating system of the FPGA-SoC, hardware. … … 25 27 transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for 26 28 their FPGA and that GPU HPC softwares use also it. 27 \mustbecompleted { FIXME :: ai supprime (mis en commentaire) la phrse qui suivait}28 29 %This will allow us at least to be inspired by GPU communication schemes and may be to reuse 29 30 %parts of the GPU softwares. … … 37 38 the application part running on the FPGA-SoC. 38 39 \begin{livrable} 39 \itemL{0}{6}{d}{\S upmc}{HPC communication API}{1.0:0:0}40 \itemL{0}{6}{d}{\Sbull}{HPC communication API}{1.0:0:0} 40 41 \setMacroInAuxFile{hpcCommApi} 41 42 Specification describing the API.
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