- Timestamp:
- Feb 13, 2010, 9:40:48 PM (15 years ago)
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- anr
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anr/anr.bib
r123 r135 73 73 } 74 74 75 @InProceedings{cosy, 76 author = { J.Y Brunel, al }, 77 title = { COSY: a methodology for system design based on reusable hardware \& software IP's}, 78 booktitle = { Technologies for the Information Society }, 79 publisher = { IOS Press }, 80 year = {1998}, 81 pages = {709-716}, 82 } 83 75 84 @InProceedings{disydent05, 76 85 author = {{Ivan Aug\'{e}, Fr\'{e}d\'{e}ric P\'{e}trot, Franï¿œois Donnet and Pascal Gomez}}, … … 81 90 year = {2005}, 82 91 } 92 @inproceedings{dspin08, 93 author = {Miro-Panades, Ivan and Clermidy, Fabien and Vivet, Pascal and Greiner, Alain}, 94 title = {Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture}, 95 booktitle = {NOCS '08: Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip}, 96 year = {2008}, 97 isbn = {978-0-7695-3098-7}, 98 pages = {139--148}, 99 publisher = {IEEE Computer Society}, 100 address = {Washington, DC, USA}, 101 } 102 83 103 84 104 % HLS -
anr/section-2.2.tex
r134 r135 105 105 Regarding system level architecture, the project is based on the know-how 106 106 acquired by the \upmc and \tima laboratories in the framework of various projects 107 (COSY~\cite{disydent}, or MEDEA-MESA~\cite{dspin}), in the field of communication108 architectures for shared memory multi-processors systems.109 As an example, the DSPIN network on chip, is now used by BULLin the TSAR project.107 in the field of communication architectures for shared memory multi-processors systems 108 (COSY~\cite{cosy}, DISYDENT~\cite{disydent05} or DSPIN~\cite{dspin08} of MEDEA-MESA). 109 As an example, the DSPIN project is now used in the TSAR project. 110 110 \item 111 111 Regarding Application Specific Instruction Processor (ASIP) design, the
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