Changeset 134 for anr


Ignore:
Timestamp:
Feb 13, 2010, 3:24:29 PM (15 years ago)
Author:
coach
Message:

IA: fixed mutek, altera, xilinx, and neutal architectural template

Location:
anr
Files:
15 edited

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  • anr/section-1.tex

    r100 r134  
    7171    architectural template and the target FPGA device.
    7272\item[Hardware/Software communication middleware:]
    73     Coach will implement an homogeneous HW/SW communication infrastructure and
     73    COACH will implement an homogeneous HW/SW communication infrastructure and
    7474    communication APIs (Application Programming Interface), that will be used for
    7575    communications between software tasks running on embedded processors and
    … …  
    9797It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
    9898
    99 \mustbecompleted{FIXME == SUPPRIMER LE H de Mutek ???}
    100 (DSX, component library), operating systems (MutekH, DNA/OS).
     99(DSX, component library), operating systems (MUTEKH, DNA/OS).
    101100It also leverages on  several existing technologies:
    102101on the GAUT~\cite{gaut08} and UGH~\cite{ugh08} tools for HLS,

  • anr/section-2.1.tex

    r99 r134  
    3838choice for low-to-medium volume applications.
    3939Since their introduction in the mid eighties, FPGAs evolved from a simple,
    40 low-capacity gate array to devices (\altera STRATIX III, Xilinx Virtex V) that
     40low-capacity gate array to devices (\altera STRATIX III, \xilinx Virtex V) that
    4141provide a mix of coarse-grained data path units, memory blocks, microprocessor cores,
    4242on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
    … …  
    7474software library that reflect the hardware configuration.
    7575%% Steven disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this.
    76 %% IA: ces lignes ont ete verifiees et corrigée pa altera. De plus C2H est plutot limite.
     76%% IA: ces lignes ont ete verifiees et corrigée pa \altera. De plus C2H est plutot limite.
    7777Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to
    7878simulate the platform at a high design level (systemC).
    … …  
    9696\begin{enumerate}
    9797  \item a virtual prototyping environment such as SoCLib for system level exploration,
    98   \item an architecture compiler (such as SOPC Builder from \altera, or System generator from Xilinx)
    99         to define the hardware architecture,
     98  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
     99  from \xilinx) to define the hardware architecture,
    100100  \item one or several HLS tools (such as PICO~\cite{pico} or CATAPULT-C~\cite{catapult-c}) for
    101101        coprocessor synthesis,

  • anr/section-2.2.tex

    r120 r134  
    77The COACH project answers to several of the challenges found in different axis of the call for proposals. Keywords of the call are indicated below in italic writing.
    88
    9 Axis 1 "Architectures des systemes embarque" :
     9Axis 1 "Architectures des syst\`{e}mes embarqu\'{e}s" :
    1010
    1111COACH will address new embedded systems architectures by allowing the design of  Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design constraints and objectives (real-time, low-power). It will permit to design  complex SoC  based on IP cores ((memory, peripherals, network controllers, communication processors), running Embedded Software, as well as an Operating System with associated middleware and API and using hardware accelerator automatically generated. It will also permit to use efficiently different dynamic system management techniques and re-configuration mechanisms.

  • anr/section-2.tex

    r99 r134  
    5050in a plat-form based design flow supporting virtual prototyping and design space exploration.
    5151Most building blocks already exist (resulting from previous projects): the GAUT
    52 or UGH synthesis tools, the MutekH or DNA embedded operating systems, the ASIP technology,
     52or UGH synthesis tools, the MUTEKH or DNA embedded operating systems, the ASIP technology,
    5353the DSX exploration tool, the MWMR hardware/software communication middleware, the BEE parallelisation tool,
    5454as well as the SoCLib library of systemC simulation models. They must now be integrated in
    … …  
    8888%\textbf{High Level Synthesis}: When dedicated hardware coprocessors have been
    8989%identified as mandatory, they will be generated by the high level synthesis (HLS) tools.
    90 %The Coach framework will integrate various HLS tools, supporting the micro-architectural space
     90%The COACH framework will integrate various HLS tools, supporting the micro-architectural space
    9191%design exploration. Here again, the exploration criteria are cost, throughput, latency
    9292%and power consumption.

  • anr/section-3.1.tex

    r120 r134  
    5454cover the whole system synthesis process in a full automatic way. Moreover,
    5555they are bound to a particular device family and to IPs library.
    56 The most commonly used are provided by Altera and Xilinx to promote their
     56The most commonly used are provided by \altera and \xilinx to promote their
    5757FPGA devices. These two representative tools used to synthesize SoC on FPGA
    5858are introduced below.
    5959\\
    60 The Xilinx System Generator for DSP~\cite{system-generateur-for-dsp} is a
     60The \xilinx System Generator for DSP~\cite{system-generateur-for-dsp} is a
    6161plug-in to Simulink that enables designers to develop high-performance DSP
    62 systems for Xilinx FPGAs.
     62systems for \xilinx FPGAs.
    6363Designers can design and simulate a system using MATLAB and Simulink. The
    6464tool will then automatically generate synthesizable Hardware Description
    65 Language (HDL) code mapped to Xilinx pre-optimized algorithms.
    66 However, this tool targets only DSP based algorithms, Xilinx FPGAs and
     65Language (HDL) code mapped to \xilinx pre-optimized algorithms.
     66However, this tool targets only DSP based algorithms, \xilinx FPGAs and
    6767cannot handle a complete SoC. Thus, it is not really a system synthesis tool.
    6868\\
    … …  
    7070system, to synthesis it, to programm it into a target FPGA and to upload a
    7171software application.
    72 % FIXME(C2H from Altera, marche vite mais ressource monstrueuse)
     72% FIXME(C2H from \altera, marche vite mais ressource monstrueuse)
    7373Nevertheless, SOPC Builder does not provide any facilities to synthesize
    7474coprocessors. System Designer must provide the synthesizable description
    … …  
    7777accurate level.
    7878\\
    79 In addition, Xilinx System Generator and SOPC Builder are closed world
     79In addition, \xilinx System Generator and SOPC Builder are closed world
    8080since each one imposes their own IPs which are not interchangeable.
    8181
    … …  
    9898Moreover, low power consumption constraint is mandatory for embedded systems.
    9999However, it is not yet well handled or not handle at all by the synthesis tools already available.
    100 \item The parallelism is extracted from initial algorithmic specification. To get more parallelism or to reduce
    101 the amount of required memory in the SoC, the user must re-write the algorithmic specification while there is
    102 techniques as polyedric transformations to increase the intrinsic parallelism.
    103 \item While they support limited loop transformations like loop unrolling and loop pipelining, current HLS tools
    104 do not provide support for design space exploration neither through automatic loop transformations nor through
    105 memory mapping.
     100\item The parallelism is extracted from initial algorithmic specification.
     101To get more parallelism or to reduce the amount of required memory in the SoC, the user
     102must re-write the algorithmic specification while there is techniques as polyedric
     103transformations to increase the intrinsic parallelism.
     104\item While they support limited loop transformations like loop unrolling and loop
     105pipelining, current HLS tools do not provide support for design space exploration neither
     106through automatic loop transformations nor through memory mapping.
    106107\item Despite they have the same input language (C/C++), they are sensitive to the style in
    107108which the algorithm is written. Consequently, engineering work is required to swap from

  • anr/section-3.2.tex

    r104 r134  
    83833 architectural templates that are synthesizable and that can be prototyped,
    8484one design space exploration tool,
    85 2 operating systems (DNA/OS and MUTEK.
     852 operating systems (DNA/OS and MUTEKH.
    8686\\
    8787The framework fonctionality will be demonstrated with the demonstrators

  • anr/section-4.1.tex

    r132 r134  
    3232hardware) either as a SystemC simulator to prototype and explore quickly the
    3333design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
    34 launch the Xilinx or Altera RTL synthesis tools.} directly downloadable on the
     34launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the
    3535FPGA device\footnote{Additional partial bitstreams are generated in case of
    3636 dynamic partial reconfiguration}.
    37 %To proove CSG that COACH is open and CSG is really configurable, COACH will
    38 %basically support 3 architecture template (the COACH template based on a
    39 %MIPS processors and a VCI token ring, the Altera template based on the NIOS
    40 %and AVALON bus, the Xilinx template based on the MICROBLAZE and PLB bus)
    41 %and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced
    42 %by the \mustbecompleted{FIXME:zied} contribution that consists in
    43 %implementing an other hardware target.
    44 %\\
    45 %Finally, it is important to notice that this work is a strong
    46 %enhancement of the SocLib software.
    4737\parlf
    4838The software architecture for HAS is presented in figure~\ref{archi-hls}.

  • anr/section-4.4.tex

    r132 r134  
    3636    written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC.
    3737    The main restrictions are:
    38     1) only the COACH architectural template is supported,
     38    1) only the neutral architectural template is supported,
    3939    2) HAS is not available (but prototyping with virtual coprocessors is available),
    4040    3) Enhanced communication schemes are not available.
    4141\item[Milestone 3 ($T0+18$)]  The second COACH release. At this step most of the COACH
    4242    features are availables.
    43     The main restriction is that COACH can not yet generate FPGA-SoC for ALTERA and XILINX
    44     architectural templates.
     43    The main restriction is that COACH can not yet generate FPGA-SoC for \altera and
     44    \xilinx architectural templates.
    4545    The others restriction is that the HAS tools are not yet fully operational.
    4646\item[Milestone 4 ($T0+24$)] The pre-release of the COACH project. The full design flow is
    … …  
    7373%       Our experience with UGH and GAUT give us confidence in the succes of this
    7474%       task.
    75 \item[Virtual prototyping of ALTERA \& XILINX architectural templates ({\csgAlteraSystemC},
     75\item[Virtual prototyping of \altera \& \xilinx architectural templates ({\csgAlteraSystemC},
    7676     {\csgXilinxSystemC})]
    7777     The SocLib component library contains several SystemC models used for the virtual
    78      prototyping of the ALTERA and XILINX architectural templates (NIOS and Microblaze processor cores).
     78     prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores).
    7979     Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped.
    8080     If the workload of this simulation model development is too important, virtual prototyping
    … …  
    8585     If one of these tasks is impossible or too important or leads to inefficiency,
    8686     it will be abandoned.
    87      In this case, the COACH architectural template will not be available for HPC and
     87     In this case, the neutral architectural template will not be available for HPC and
    8888     a SystemC VCI model corresponding to the PCI/X IP will be developped to allow
    8989     virtual prototyping.

  • anr/section-5.tex

    r126 r134  
    11\subsection{Dissemination}
    22
    3 The Coach project will bring new scientific results in various fields, such as high level synthesis,
     3The COACH project will bring new scientific results in various fields, such as high level synthesis,
    44hardware/software codesign, virtual prototyping, harware oriented compilation techniques,
    55automatic parallelisation, etc. These results will be presented in the relevant International
    66Conferences, namely DATE, DAC, or ICCAD.
    77
    8 More generally, the Coach infrastructure and the design flow supported by the Coach
     8More generally, the COACH infrastructure and the design flow supported by the COACH
    99tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis
    1010in various worshops and conferences.
    1111
    1212Following the general policy of the SoCLib platform, the COACH project will be an
    13 open infrastructure, and the Coach tools and libraries will available in the framework
     13open infrastructure, and the COACH tools and libraries will available in the framework
    1414of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory.
    1515
    1616\subsection{Exploitation of results}
    1717
    18 The main goal of the Coach project is to help SMEs (Small and Medium Enterprises)
     18The main goal of the COACH project is to help SMEs (Small and Medium Enterprises)
    1919to enter the world of MPSoC technologies. For small companies, the cost is a primary concern.
    2020Moreover, these companies have not always in-home expertise in hardware design and VHDL modelling.
    21 As the fabrication costs of an ASIC is generally too high for SMEs, the Coach project focus
     21As the fabrication costs of an ASIC is generally too high for SMEs, the COACH project focus
    2222on FPGA technologies. Regarding the design tools, the cost of advanced ESL (Electronic System Design)
    23 tools is an issue, and the Coach project will follow the same general policy as the SoCLib platform :
     23tools is an issue, and the COACH project will follow the same general policy as the SoCLib platform :
    2424
    2525\begin{itemize}
    2626\item
    27 All software tools supporting the Coach design flow will be available as free software.
    28 All academic partners contributing to the Coach project agreed to distribute the ESL software
     27All software tools supporting the COACH design flow will be available as free software.
     28All academic partners contributing to the COACH project agreed to distribute the ESL software
    2929tools under the same GPL license as the SoCLib tools. 
    3030\item
    … …  
    4242For commercial use, commercial licenses will be negociated between the owners and the customers.
    4343\item
    44 The proprietary ALTERA, XILINX and FLEXRAS IP core libraries are commercial products
     44The proprietary \altera, \xilinx and \zied IP core libraries are commercial products
    4545that are not involved by the free software policy, but these libraries will be supported by the
    46 synthesis tools developped in the Coach project.
     46synthesis tools developped in the COACH project.
    4747\end{itemize}
    4848
    … …  
    5959
    6060A global consortium agreement will be defined during the first six monts of the project.
    61 As already stated, the Coach project has been prepared during one year by a monthly meeting
     61As already stated, the COACH project has been prepared during one year by a monthly meeting
    6262involving the five academic partners. The general free software policy described in the
    6363previous section has been agreed by academic partners  and has been

  • anr/section-6.1.tex

    r132 r134  
    150150Moreover, the LIP6 developped during the last 10 years the UGH tool for high level synthesis
    151151of control-dominated coprocessors.
    152 This tool will be modified to be integrated in the Coach design flow.
    153 \parlf
    154 Even if the preferred dissemination policy for the Coach design flow will be the free software policy,
     152This tool will be modified to be integrated in the COACH design flow.
     153\parlf
     154Even if the preferred dissemination policy for the COACH design flow will be the free software policy,
    155155(following the SoCLib model), the SoC department is ready to support start-ups : Six startup companies
    156156(including \zied) have been created by former researchers from  the SoC department of LIP6 between 1997 and 2002.

  • anr/section-6.2.tex

    r132 r134  
    1 The Coach project will be coordinated by professor Alain Greiner from
     1The COACH project will be coordinated by professor Alain Greiner from
    22Université Pierre et Marie Curie.
    33Alain Greiner is the initiator and the main architect of the SoCLib project.
    44This ANR platform for virtual prototyping of MPSoCs involved 6 industrial companies
    55(including ST Microelectronics and Thales) and ten academic laboratories
    6 (5 of them are involved in the Coach project).
     6(5 of them are involved in the COACH project).
    77The SoCLib project was managed by Thales, but the technical coordination has been done
    88by Alain Greiner, who has a good experience in coordinating large technical projects

  • anr/task-2.tex

    r126 r134  
    2424to allow the demonstrators to start working.
    2525This release will include the standard communication schemes (base on SocLib MWMR component)
    26 and support the COACH architectural template for prototyping and hardware generation.
     26and support the neutral architectural template for prototyping and hardware generation.
    2727\end{objectif}
    2828%
    2929\begin{workpackage}
    30 \subtask This \ST corresponds to the Coach System Generator (CSG) software.
     30\subtask This \ST corresponds to the COACH System Generator (CSG) software.
    3131    \begin{livrable}
    3232    \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
    33         The first software release of the CSG tool that will allow demonstrators to start working by using the COACH
    34         hardware architecture template.
     33        The first software release of the CSG tool that will allow demonstrators to start
     34        working by using the neutral architectural template.
    3535    \itemV{12}{18}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgPrototypingOnly}
    36         The second release of CSG supports the XILINX and ALTERA architectural
     36        The second release of CSG supports the \xilinx and \altera architectural
    3737        templates and the enhanced communication system, but only for SystemC prototyping.
    3838        This release integrates a first integration of HLS tools.
    3939    \itemV{18}{24}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgAllArch}
    4040        This milestone extends CSG (\csgPrototypingOnly) to
    41         FPGA-SoC generation for the XILINX and ALTERA architectural template.
     41        FPGA-SoC generation for the \xilinx and \altera architectural template.
    4242    \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:6}
    4343        Final release of CSG.
    … …  
    4545\subtask This \ST deals with the components of the architectural templates.
    4646    \\
    47     For the COACH architectural template, it consists of the development of the VHDL
     47    For the neutral architectural template, it consists of the development of the VHDL
    4848    synthesizable description of the missing communication components (MWMR)
    4949        in order to support the process network communication model.
    … …  
    5252    ANR project.
    5353    \\
    54     For the XILINX and ALTERA architectural templates, we use the XILINX and ALTERA IPs (NIOS, Microblaze, memories, busses...).
     54    For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...).
    5555    \begin{livrable}
    56     \itemL{0}{12}{h}{\Supmc}{COACH architecture}{1:0:0}
     56    \itemL{0}{12}{h}{\Supmc}{neutral architecture}{1:0:0}
    5757        \setMacroInAuxFile{csgCoachArchTempl}
    5858        The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
    5959    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
    6060       This deliverable consists in optimizing the VHDL descriptions of the components of
    61        the COACH architectural template (deliverable \novers{\csgCoachArchTempl}) to the
     61       the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
    6262       \xilinx RTL synthesis tools.
    6363       \upmc will provide the VHDL descriptions, \xilinx will provide back a documentation
    6464       listing that proposes VHDL generation enhancements.
    65     \itemV{6}{18}{x}{\Stima}{XILINX architecture}
     65    \itemV{6}{18}{x}{\Stima}{\xilinx architecture}
    6666        \setMacroInAuxFile{csgXilinxSystemC}
    6767        The SystemC simulation module of the MWMR component with a PLB bus interface plus
    68         the SystemC modules of the components of the XILINX architectural template
     68        the SystemC modules of the components of the \xilinx architectural template
    6969        currently not available in the SocLib component library.
    70     \itemL{18}{24}{h}{\Stima}{XILINX architecture}{9:9:0}
     70    \itemL{18}{24}{h}{\Stima}{\xilinx architecture}{9:9:0}
    7171        The synthesizable VHDL description of the MWMR component corresponding to the
    7272        SystemC module of the former delivrable (\csgXilinxSystemC).
    … …  
    7676       \tima will provide MWMR VHDL description, \xilinx will provide back a documentation
    7777       listing that proposes VHDL generation enhancements.
    78     \itemV{6}{18}{x}{\Sirisa}{ALTERA architecture}
     78    \itemV{6}{18}{x}{\Sirisa}{\altera architecture}
    7979        \setMacroInAuxFile{csgAlteraSystemC}
    8080        The SystemC simulation module of the MWMR component with an AVALON bus interface plus
    81         the SystemC modules of the components of the ALTERA architectural template
     81        the SystemC modules of the components of the \altera architectural template
    8282        currently not available in the SocLib component library.
    83     \itemL{18}{24}{h}{\Sirisa}{ALTERA architecture}{6:6:0}
     83    \itemL{18}{24}{h}{\Sirisa}{\altera architecture}{6:6:0}
    8484        The synthesizable VHDL description of the MWMR component corresponding to the
    8585        SystemC module of the former delivrable (\csgAlteraSystemC);
    … …  
    100100       listing that proposes VHDL generation enhancements.
    101101    \end{livrable}
    102 \subtask This \ST consists of the configuration of the SocLib MUTEK and DNA operating
     102\subtask This \ST consists of the configuration of the SocLib MUTEKH and DNA operating
    103103    system and the development of drivers for the hardware architectural templates
    104104    and enhanced communication schemes defined in \novers{\specCsgManual} delivrable.
    105     For the ALTERA and XILINX architectural templates, the OSs must also be ported on
     105    For the \altera and \xilinx architectural templates, the OSs must also be ported on
    106106    the NIOS2 and MICROBLAZE processors.
    107107    \begin{livrable}
    108     \itemV{6}{8}{x}{\Supmc}{MUTEK OS}
     108    \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
    109109        The drivers required for the first CSG milestone (delivrable \csgCoachArch).
    110     \itemV{8}{18}{x}{\Supmc}{MUTEK 0S}
     110    \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S}
    111111        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
    112     \itemL{18}{33}{x}{\Supmc}{MUTEK OS}{1:1:2}
     112    \itemL{18}{33}{x}{\Supmc}{MUTEKH OS}{1:1:2}
    113113        Maintenance work.
    114     \itemL{6}{18}{x}{\Supmc}{Port of MUTEK OS}{1.0:1:0}
    115         Porting of MUTEK OS on the NIOS2 and MICROBLAZE processors.
     114    \itemL{6}{18}{x}{\Supmc}{Port of MUTEKH OS}{1.0:1:0}
     115        Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
    116116    \itemV{6}{8}{x}{\Stima}{DNA OS}
    117117        The drivers required for the first CSG milestone (delivrable \csgCoachArch).

  • anr/task-3.tex

    r126 r134  
    4949      \itemL{0}{12}{X}{\Sirisa}{SystemC for NIOS processor}{2:0:0}
    5050          { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
    51           already available from Altera}
     51          already available from \altera}
    5252      \itemV{12}{18}{H}{\Sirisa}{VHDL for an extensible MIPS}
    5353      {A synthesizable VHDL model for a simple extensible MIPS architectural template}

  • anr/task-5.tex

    r130 r134  
    2525
    2626The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
    27 transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for
     27transfers. The reasons of this choices are that both \altera and \xilinx provide PCI/X IP for
    2828their FPGA and that GPU HPC softwares use also it.
    2929%This will allow us at least to be inspired by GPU communication schemes and may be to reuse
    … …  
    5858        The PC part of the HPC communication API that comminicates with the FPGA-SOC, a
    5959        library and probably a LINUX module.
    60     \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEK OS}{0:3:0}
     60    \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEKH OS}{0:3:0}
    6161        \setMacroInAuxFile{hpcMutekDriver}
    6262        The FPGA-SoC part of the communication API, a driver.
    … …  
    6464        Port of the {\hpcMutekDriver} driver on the DNA OS.
    6565    \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
    66         Maintenance work of HPC API for both Linux PC and MUTEK OS.
     66        Maintenance work of HPC API for both Linux PC and MUTEKH OS.
    6767    \end{livrable}
    6868\subtask This \ST deals with the implementation of hardware and SystemC modules
    69     required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx.
     69    required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx.
    7070    \begin{livrable}
    7171    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
    … …  
    9494            The drivers required by the DNA OS in order to manage dynamic partial
    9595        reconfiguration inside the SoC-FPGA.
    96     \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1}
    97         Port of the {\hpcDynconfDriver} drivers on the MUTEK OS.
     96    \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEKH drivers}{0:0:1}
     97        Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
    9898    \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
    9999        Extension of the HPC partionning helper in order to integrate dynamic partial

  • anr/task-6.tex

    r129 r134  
    116116        This delivrable is a VHDL description.
    117117%      \itemL{12}{18}{x}{\Szied}{bitstream loader port}{0:3.6:0}
    118 %        Port of the bitstream loader to the MUTEK operating system.
     118%        Port of the bitstream loader to the MUTEKH operating system.
    119119      \itemL{18}{24}{x}{\Szied}{\zied demonstrators}{0:2.4:0}
    120120        \zied will propose to test COACH framework and the \zied architecture template
    121121        throught a basic application.
    122         This applicattion will containt 3 communicating tasks under the coach format specified
     122        This applicattion will containt 3 communicating tasks under the COACH format specified
    123123        in {\novers{\specGenManual}} delivrable.
    124124        The first one is a hardware task generated by the HAS tools and transformed into
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