Changeset 143


Ignore:
Timestamp:
Feb 14, 2010, 10:32:11 AM (14 years ago)
Author:
coach
Message:

IA: upadted Xilinx data

Location:
anr
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • anr/section-7.tex

    r131 r143  
    209209    The travel costs are associated to project meeting as well as participation to
    210210    conferences. The travel costs are estimated to
    211     \mustbecompleted{FIXME:\xilinx: XX\%} of the total requested ANR funding.
     211    2\% of the total requested ANR funding.
    212212\item[Expenses for inward billing] none
    213213\item[Other working costs] none

  • anr/task-2.tex

    r134 r143  
    7171        The synthesizable VHDL description of the MWMR component corresponding to the
    7272        SystemC module of the former delivrable (\csgXilinxSystemC).
    73     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:2}
     73    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5}
    7474       This deliverable consists in optimizing the MWMR VHDL description (deliverable
    7575       \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
    … …  
    9292       and its corresponding SystemC module.
    9393    \itemL{24}{30}{x}{\Subs}{UBS communication adapter}{0:0:0}
    94        Final release of the tool that generates the VHDL description of the optimized communication adapter
    95        and its corresponding SystemC module (\gautCOMMoptimization).
    96     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:2}
     94       Final release of the tool that generates the VHDL description of the optimized
     95       communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
     96    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5}
    9797       This deliverable consists in optimizing the communication adapter VHDL description (deliverable
    9898       \novers{\gautCOMMoptimization}).

  • anr/task-4.tex

    r126 r143  
    7777        informations in order to explore the design space and to generate optimized architectures.
    7878    \itemL{18}{30}{x}{\Subs}{Design Space Exploration}{0:0:0}
    79         Release of the GAUT software that supports the features defined in \ST ????.
     79        Release of the GAUT software that supports the features defined in
     80        \mustbecompleted{FIXME:UBS: macro ????} delivrable.
    8081    \end{livrable}
    8182\subtask In FPGA-SoC, the frequency is given by the processor(s) and the system BUS. The coprocessors
    … …  
    9697        The frequency calibration software consists of a driver in the FPGA-SoC operating
    9798        system and of a control software.
    98     \itemL{24}{27}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (5)}{0:0:1}
     99    \itemL{24}{27}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (5)}{0:0:1.5}
    99100       This deliverable consists in optimizing the VHDL description provided in
    100101       \novers{\freqCalibrationVhdl}.

  • anr/task-5.tex

    r141 r143  
    4545    It is a library implementing the communication API with features to profile
    4646    the partitioned application.
    47 %FIXME (Olivier) pour moi, on veut un outil de profiling pour partitionner l'application.
    48 % It is a profiling (or simulation) library implementing the communication API
    49 
    5047    \begin{livrable}
    5148    \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0}
    … …  
    10097        reconfiguration dedicated features (reconfiguration time of regions, variable
    10198        number of coprocessors).
    102     \itemL{24}{36}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx dynamic reconfiguration}{0:0:1}
     99    \itemL{24}{36}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx dynamic reconfiguration}{0:0:2}
    103100        \xilinx will work with \tima in order to better take into account during
    104101        partitioning decisions specific constraints due to partial reconfiguration process.

  • anr/task-7.tex

    r130 r143  
    5454        how a promising task graph can be obtained.
    5555    \itemV{18}{24}{d}{\Supmc}{tutorial}
    56     \mustbecompleted{FIXME: LIP6 :: Avons (UBS) change le lead du livrable OK ?}
    57     \mustbecompleted{FIXME: LIP6 :: C'est pas possible, car il faut changer aussi
    58     au-dessus c'est le meme livrable en 3 fois. De plus la c'est plus une DOC CSG que
    59     HAS.}
     56%    \mustbecompleted{FIXME: LIP6 :: Avons (UBS) change le lead du livrable OK ?}
     57%    \mustbecompleted{FIXME: LIP6 :: C'est pas possible, car il faut changer aussi
     58%    au-dessus c'est le meme livrable en 3 fois. De plus la c'est plus une DOC CSG que HAS.}
    6059        This tutorial shows how a task can be migrated to coprocessor using HAS tools and
    6160        how FPGA-SoC can be generated and run to FPGA. This for HAS tools and and
    … …  
    6362    \itemL{30}{36}{d}{\Supmc}{tutorial}{2:1:1}
    6463        The final release of the tutorial.
    65     \itemL{30}{33}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (6)}{0:0:1}
     64    \itemL{30}{33}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (6)}{0:0:0.5}
    6665        \xilinx will check that developped tutorial works well with \xilinx tools,
    6766        and will propose corrections or enhancements if needed into a document.
Note: See TracChangeset for help on using the changeset viewer.