Changeset 143 for anr/task-2.tex

Timestamp:

Feb 14, 2010, 10:32:11 AM (14 years ago)

Author:

coach

Message:

IA: upadted Xilinx data

File:

• anr/task-2.tex (modified) (2 diffs)

anr/task-2.tex

@@ -71 +71 @@
         The synthesizable VHDL description of the MWMR component corresponding to the
         SystemC module of the former delivrable (\csgXilinxSystemC).
-    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:2}
+    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5}
        This deliverable consists in optimizing the MWMR VHDL description (deliverable
        \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
@@ -92 +92 @@
        and its corresponding SystemC module. 
     \itemL{24}{30}{x}{\Subs}{UBS communication adapter}{0:0:0}
-       Final release of the tool that generates the VHDL description of the optimized communication adapter
-       and its corresponding SystemC module (\gautCOMMoptimization).
-    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:2}
+       Final release of the tool that generates the VHDL description of the optimized
+       communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
+    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5}
        This deliverable consists in optimizing the communication adapter VHDL description (deliverable
        \novers{\gautCOMMoptimization}).