Changeset 152 for anr/task-3.tex

Timestamp:

Feb 15, 2010, 8:50:43 AM (14 years ago)

Author:

coach

Message:

IA: fixed typos and added lip tables

File:

• anr/task-3.tex (modified) (4 diffs)

anr/task-3.tex

@@ -26 +26 @@
   instructions definitions along with their occurrence in the application.
     \begin{livrable}
-      \itemV{0}{18}{X}{\Sirisa}{ASIP compilation flow}
+      \itemV{0}{18}{x}{\Sirisa}{ASIP compilation flow}
         In this first version of the software, the computations patterns corresponding to
         custom instructions are specified by the user, and then automatically extracted (when
         beneficial) from the application intermediate representation. 
         %\mustbecompleted{FIXME .....}
-      \itemL{18}{24}{X}{\Sirisa}{ASIP compilation flow}{6:9:0}
+      \itemL{18}{24}{x}{\Sirisa}{ASIP compilation flow}{6:9:0}
         In this second version, the software will also be able to automatically identify 
         interesting pattern candidates in the application code, and use them as custom 
@@ -42 +42 @@
  of the architecture, along with its architectural extensions 
     \begin{livrable}
-      \itemV{0}{12}{X}{\Sirisa}{SystemC for extensible MIPS }
+      \itemV{0}{12}{x}{\Sirisa}{SystemC for extensible MIPS }
       { A SystemC simulation model for a simple extensible MIPS architectural template }
-      \itemL{12}{20}{X}{\Sirisa}{SystemC for extensible MIPS}{2:3:0}
+      \itemL{12}{20}{x}{\Sirisa}{SystemC for extensible MIPS}{2:3:0}
       {A SystemC simulation model for an extensible MIPS with a tight architectural integration of
       its instruction set extensions}
-      \itemL{0}{12}{X}{\Sirisa}{SystemC for NIOS processor}{2:0:0}
+      \itemL{0}{12}{x}{\Sirisa}{SystemC for NIOS processor}{2:0:0}
           { A SystemC simulation model for an extensible NIOS processor template, the VHDL model being
           already available from \altera}
-      \itemV{12}{18}{H}{\Sirisa}{VHDL for an extensible MIPS}
+      \itemV{12}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
       {A synthesizable VHDL model for a simple extensible MIPS architectural template}
-      \itemL{18}{24}{H}{\Sirisa}{VHDL for an extensible MIPS}{9:12:0}
+      \itemL{18}{24}{h}{\Sirisa}{VHDL for an extensible MIPS}{9:12:0}
       {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
       its instruction set extensions}
-      \itemL{24}{36}{D}{\Sirisa}{Evaluation report }{0:0:2}
+      \itemL{24}{36}{d}{\Sirisa}{Evaluation report }{0:0:2}
       {An evaluation report with quantitative analysis of the performance/area trade-off induced by
       the different approaches}
@@ -67 +67 @@
       polyhedral loops. User manual. 
       \mustbecompleted{ FIXME :: User manual ou Specification. Si user manual alors le mettre en dissemination}
-    \itemL{30}{36}{d}{\Slip}{Process generation method}{0:0:0}
+    \itemL{30}{36}{d}{\Slip}{Process generation method}{4.5:0.0:10.5}
       Final assessment of the method and improved version of the user manual.
       \mustbecompleted {FIXME :: User manual ou Specification. Si user manual alors le mettre en dissemination}
@@ -79 +79 @@
       Extension of automatic parallelization and array contraction
       to non-polyhedral loops. Implementation in the Bee framework.
-    \itemL{30}{36}{x}{\Slip} {Process and FIFO construction}{0:0:0}
+    \itemL{30}{36}{x}{\Slip} {Process and FIFO construction}{4.5:12.0:15.0}
       Final release taking into account the feedbacks from the 
       demonstrator \STs.