Changeset 180


Ignore:
Timestamp:
Feb 15, 2010, 3:53:53 PM (15 years ago)
Author:
coach
Message:

UBS

Location:
anr
Files:
2 edited

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  • anr/anr.bib

    r174 r180  
    144144%%% UBS
    145145
     146@INBOOK{IEEEDT,
     147author = {Philippe Coussy and Andres Takach},
     148title = {Special Issue on High-Level Synthesis},
     149journal ={IEEE Design and Test of Computers},
     150volume = {25},issn = {0740-7475},
     151year = {2008},
     152pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
     153publisher = {IEEE Computer Society},
     154address = {Los Alamitos, CA, USA},}
     155
     156
     157@INBOOK{HLSBOOK,
     158  author    = {P. Coussy and A. Morawiec},
     159  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
     160  publisher = {Springer},
     161  year      = {2008},
     162}
     163
     164@INBOOK{CATRENE,
     165  author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
     166  booktitle = {European Roadmap for EDA},
     167  publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
     168  year      = {2009},
     169}
     170
     171
     172@INBOOK{IEEEDT,
     173author = {Philippe Coussy and Andres Takach},
     174title = {Special Issue on High-Level Synthesis},
     175journal ={IEEE Design and Test of Computers},
     176volume = {25},issn = {0740-7475},
     177year = {2008},
     178pages = {393},doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.147},
     179publisher = {IEEE Computer Society},
     180address = {Los Alamitos, CA, USA},}
     181
     182
     183@INBOOK{HLSBOOK,
     184  author    = {P. Coussy and A. Morawiec},
     185  booktitle = {High-Level Synthesis: From Algorithm to Digital Circuits},
     186  publisher = {Springer},
     187  year      = {2008},
     188}
     189
     190@INBOOK{CATRENE,
     191  author    = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
     192  booktitle = {European Roadmap for EDA},
     193  publisher = {CATRENE, Cluster for Application and Technology Research in Europe on NanotElectronics},
     194  year      = {2009},
     195}
    146196
    147197@INBOOK{gaut08,
  • anr/section-3.1.tex

    r174 r180  
    2626Finally, efficient design methodology are required in order to
    2727hide FPGA complexity and the underlying implantation subtleties to HPC users,
    28 so that they don't have to change their habits and can have equivalent design productivity
     28so that they do not have to change their habits and can have equivalent design productivity
    2929than in others families~\cite{hpc07a}.
    3030
     
    3939Mitrionics has an elegant solution based on a compute engine specifically
    4040developed for high-performance execution in FPGAs. Unfortunately, the design flow
    41 is based on a new programming language (mitrionC) implying designer efforts and poor portability.
     41is based on a new programming language (mitrionC) implying important designer efforts and poor portability.
    4242% tool relying on operator libraries (XtremeData), 
    4343% Parle t-on de l'OPenFPGA consortium, dont le but est : "to accelerate the incorporation of reconfigurable computing technology in high-performance and enterprise applications" ?
     
    7474coprocessors. System Designer must provide the synthesizable description
    7575with the feasible bus interface. Design Space Exploration is thus limited
    76 and SystemC simulation is not possible neither at transactional nor at Cycle
     76and SystemC simulation is not possible neither at transactional nor at cycle
    7777accurate level.
    7878\\
     
    8888academic world and CATAPULTC~\cite{catapult-c}, PICO~\cite{pico} and
    8989CYNTHETIZER~\cite{cynthetizer} in commercial world.  Despite their
    90 maturity, their usage is restrained by:
     90maturity, their usage is restrained by \cite{IEEEDT} \cite{CATRENE} \cite{HLSBOOK}:
    9191\begin{itemize}
    9292\item The HLS tools are not integrated into an architecture and system exploration tool.
    9393Thus, a designer who needs to accelerate a software part of the system, must adapt it manually
    9494to the HLS input dialect and performs engineering work to exploit the synthesis result
    95 at the system level.
     95at the system level,
     96\item They target control oriented or data oriented application only,
    9697\item HLS tools take into account only one or few constraints simultaneously while realistic
    97 designs are multi-constrained.
     98designs are multi-constrained,
    9899Moreover, low power consumption constraint is mandatory for embedded systems.
    99 However, it is not yet well handled or not handle at all by the synthesis tools already available.
    100 \item The parallelism is extracted from initial algorithmic specification.
     100However, it is not yet well handled or not handle at all by the synthesis tools already available,
     101\item The parallelism is extracted from initial algorithmic specification,
    101102To get more parallelism or to reduce the amount of required memory in the SoC, the user
    102103must re-write the algorithmic specification while there is techniques as polyedric
    103 transformations to increase the intrinsic parallelism.
     104transformations to increase the intrinsic parallelism,
    104105\item While they support limited loop transformations like loop unrolling and loop
    105106pipelining, current HLS tools do not provide support for design space exploration neither
    106 through automatic loop transformations nor through memory mapping.
     107through automatic loop transformations nor through memory mapping,
    107108\item Despite they have the same input language (C/C++), they are sensitive to the style in
    108109which the algorithm is written. Consequently, engineering work is required to swap from
    109 a tool to another.
     110a tool to another,
    110111\item They do not respect accurately the frequency constraint when they target an FPGA device.
    111112Their error is about 10 percent. This is annoying when the generated component is integrated
     
    113114\end{itemize}
    114115Regarding these limitations, it is necessary to create a new tool generation reducing the gap
    115 between the specification of an heterogeneous system and its hardware implementation.
    116 \mustbecompleted {FIXME :: Ajouter ref livre + D\&T}
     116between the specification of an heterogeneous system and its hardware implementation \cite{HLSBOOK} \cite{IEEEDT}.
    117117
    118118\subsubsection{Application Specific Instruction Processors}
     
    138138problems\cite{ARC08}.
    139139This approach however has a strong weakness, since it also significantly reduces
    140 opportunities for achieving good seedups (most speedup remain between 1.5x and
     140opportunities for achieving good speedups (most speedup remain between 1.5x and
    1411412.5x), since ISEs performance is generally tied down by I/O constraints as
    142142they generally rely on the main CPU register file to access data.
     
    156156would allow researchers and system designers to :
    157157\begin{itemize}
    158 \item Explore the various level of interactions between the original CPU micro-architecure
    159 and its extension (for example throught a Domain Specific Language targeted at micro-architecture
     158\item Explore the various level of interactions between the original CPU micro-architecture
     159and its extension (for example through a Domain Specific Language targeted at micro-architecture
    160160specification and synthesis).
    161161\item Retarget the compiler instruction-selection (or prototype nex passes) passes so as
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