Changeset 217 for anr/task-3.tex

Timestamp:

Feb 16, 2010, 11:01:26 AM (14 years ago)

Author:

coach

Message:

UBS

File:

• anr/task-3.tex (modified) (2 diffs)

anr/task-3.tex

@@ -51 +51 @@
       \itemV{12}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
       {A synthesizable VHDL model for a simple extensible MIPS architectural template}
-      \itemL{18}{24}{h}{\Sirisa}{VHDL for an extensible MIPS}{9:12:0}
+      \itemL{18}{24}{h}{\Sirisa}{VHDL for extensible MIPS}{9:12:0}
       {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
       its instruction set extensions}
@@ -76 +76 @@
       Extension of automatic parallelization and array contraction
       to non-polyhedral loops. Implementation in the Bee framework.
-    \itemL{30}{36}{x}{\Slip} {Process and FIFO construction}{20:20:20}
+    \itemL{30}{36}{x}{\Slip} {Process/FIFO construction}{20:20:20}
       Final release taking into account the feedbacks from the 
       demonstrator \STs.