- Timestamp:
- Feb 16, 2010, 1:56:18 PM (15 years ago)
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anr/task-7.tex
r211 r221 59 59 \itemL{30}{36}{d}{\Supmc}{tutorial}{2:1:1} 60 60 The final release of the tutorial. 61 \itemL{18}{24}{d}{\Stima}{ tutorial}{0:0:1}62 This tutorial shows how to generate a complete HW/SW system by using CSG tool.63 \itemL{18}{24}{d}{\Slip}{ tutorial}{0:0:0}64 This tutorial shows how to apply loop transformations to a task.65 \itemL{18}{24}{d}{\Sirisa}{ tutorial}{0:0:0}66 This tutorial shows how to customize a processor to obtain an ASIP.67 \itemL{18}{24}{d}{\Subs}{ tutorial}{0:1:0}68 This tutorial shows how a task can be synthesized by using HLS tools developped in61 \itemL{18}{24}{d}{\Stima}{CSG User manual}{0:0:1} 62 This user manual shows how to generate a complete HW/SW system by using CSG tool. 63 \itemL{18}{24}{d}{\Slip}{HAS front-end user manual}{0:0:0} 64 This user manual shows how to apply loop transformations to a task. 65 \itemL{18}{24}{d}{\Sirisa}{ASIP user manual}{0:0:0} 66 This user manual shows how to customize a processor to obtain an ASIP. 67 \itemL{18}{24}{d}{\Subs}{HLS user manual}{0:1:0} 68 This user manual shows how a task can be synthesized by using HLS tools developped in 69 69 the COACH project. 70 70 \itemL{30}{33}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (6)}{0:0:0.5}
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