Changeset 222 for anr


Ignore:
Timestamp:
Feb 16, 2010, 2:05:58 PM (15 years ago)
Author:
coach
Message:

UBS

Location:
anr
Files:
2 edited

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Unmodified
Added
Removed
  • anr/task-4.tex

    r220 r222  
    8686        A document describing the set up of the coprocessor frequency calibration.:
    8787    \itemV{12}{24}{x}{\Supmc}{Frequency calibration}
    88         \setMacroInAuxFile{FreqCalibrationVhdl}
     88        \setMacroInAuxFile{freqCalibrationVhdl}
    8989        A VHDL description of hardware added to the coprocessor to enable the calibration.
    9090    \itemL{24}{33}{x}{\Supmc}{Frequency calibration}{2:.5:3.5}
  • anr/task-7.tex

    r221 r222  
    2323    the COACH releases.
    2424    \begin{livrable}
    25       \itemV{0}{6}{d}{\Supmc}{dissemination WEB site}
     25      \itemV{0}{6}{d}{\Supmc}{Dissemination WEB site}
    2626        This deliverable consists firstly in providing a WEB site (name, HTTP server
    2727        setup, wiki) and secondly in defining the site map and finally in writting and
    2828        installing the pages.
    29       \itemL{6}{36}{d}{\Supmc}{dissemination WEB site}{1:.5:.5}
     29      \itemL{6}{36}{d}{\Supmc}{Dissemination WEB site}{1:.5:.5}
    3030        This deliverable corresponds to the standard management of a WEB site (modifying,
    3131        adding, suppressing, replacing pages).
    3232        Especialy the user reference manuals provided in the other tasks will be published
    3333        on this site. The published articles will be also be installed in this site.
    34       \itemL{6}{36}{d+x}{\Supmc}{release handling}{1:.5:.5}
     34      \itemL{6}{36}{d+x}{\Supmc}{Release handling}{1:.5:.5}
    3535        This deliverable deals with the elaboration of the COACH software milestones and
    3636        final releases with their installation manuals and to publish then into the WEB
     
    4545    The application of this tutorial will be a Motion JPEG application.
    4646  \begin{livrable}
    47     \itemV{0}{6}{x}{\Supmc}{tutorial specification}
     47    \itemV{0}{6}{x}{\Supmc}{Tutorial specification}
    4848        Choice of the application and its implementation as a C/C++ program.
    49     \itemV{6}{12}{d+x}{\Supmc}{tutorial}
     49    \itemV{6}{12}{d+x}{\Supmc}{Tutorial}
    5050        The application is split into two communicating parts, the PC part and FPGA-SoC part.
    5151        By using the features the T0+12 milestone provides,
     
    5353        The FPGA-SoC part is described as communicating task graph. The tutorial also describes
    5454        how a promising task graph can be obtained.
    55     \itemV{18}{24}{d}{\Supmc}{tutorial}
     55    \itemV{18}{24}{d}{\Supmc}{Tutorial}
    5656        This tutorial shows how a task can be migrated to coprocessor using HAS tools and
    5757        how FPGA-SoC can be generated and run to FPGA. This for HAS tools and and
    5858        architectural template available in T0+24 milestone.
    59     \itemL{30}{36}{d}{\Supmc}{tutorial}{2:1:1}
     59    \itemL{30}{36}{d}{\Supmc}{Tutorial}{2:1:1}
    6060        The final release of the tutorial.
    6161    \itemL{18}{24}{d}{\Stima}{CSG User manual}{0:0:1}
     
    6868        This user manual shows how a task can be synthesized by using HLS tools developped in
    6969                the COACH project.
    70     \itemL{30}{33}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (6)}{0:0:0.5}
     70    \itemL{30}{33}{d}{\Sxilinx}{Feedback for \ganttlf \xilinx RTL tools}{0:0:0.5}
    7171        \xilinx will check that developped tutorial works well with \xilinx tools,
    7272        and will propose corrections or enhancements if needed into a document.
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