Changeset 222 for anr/task-7.tex

Timestamp:

Feb 16, 2010, 2:05:58 PM (15 years ago)

Author:

coach

Message:

UBS

File:

• anr/task-7.tex (modified) (4 diffs)

anr/task-7.tex

@@ -23 +23 @@
     the COACH releases.
     \begin{livrable}
-      \itemV{0}{6}{d}{\Supmc}{dissemination WEB site}
+      \itemV{0}{6}{d}{\Supmc}{Dissemination WEB site}
         This deliverable consists firstly in providing a WEB site (name, HTTP server
         setup, wiki) and secondly in defining the site map and finally in writting and
         installing the pages.
-      \itemL{6}{36}{d}{\Supmc}{dissemination WEB site}{1:.5:.5}
+      \itemL{6}{36}{d}{\Supmc}{Dissemination WEB site}{1:.5:.5}
         This deliverable corresponds to the standard management of a WEB site (modifying,
         adding, suppressing, replacing pages).
         Especialy the user reference manuals provided in the other tasks will be published
         on this site. The published articles will be also be installed in this site.
-      \itemL{6}{36}{d+x}{\Supmc}{release handling}{1:.5:.5}
+      \itemL{6}{36}{d+x}{\Supmc}{Release handling}{1:.5:.5}
         This deliverable deals with the elaboration of the COACH software milestones and
         final releases with their installation manuals and to publish then into the WEB
@@ -45 +45 @@
     The application of this tutorial will be a Motion JPEG application.
   \begin{livrable}
-    \itemV{0}{6}{x}{\Supmc}{tutorial specification}
+    \itemV{0}{6}{x}{\Supmc}{Tutorial specification}
         Choice of the application and its implementation as a C/C++ program.
-    \itemV{6}{12}{d+x}{\Supmc}{tutorial}
+    \itemV{6}{12}{d+x}{\Supmc}{Tutorial}
         The application is split into two communicating parts, the PC part and FPGA-SoC part.
         By using the features the T0+12 milestone provides,
@@ -53 +53 @@
         The FPGA-SoC part is described as communicating task graph. The tutorial also describes
         how a promising task graph can be obtained.
-    \itemV{18}{24}{d}{\Supmc}{tutorial}
+    \itemV{18}{24}{d}{\Supmc}{Tutorial}
         This tutorial shows how a task can be migrated to coprocessor using HAS tools and
         how FPGA-SoC can be generated and run to FPGA. This for HAS tools and and
         architectural template available in T0+24 milestone.
-    \itemL{30}{36}{d}{\Supmc}{tutorial}{2:1:1}
+    \itemL{30}{36}{d}{\Supmc}{Tutorial}{2:1:1}
         The final release of the tutorial.
     \itemL{18}{24}{d}{\Stima}{CSG User manual}{0:0:1}
@@ -68 +68 @@
         This user manual shows how a task can be synthesized by using HLS tools developped in 
                 the COACH project. 
-    \itemL{30}{33}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx RTL tools (6)}{0:0:0.5}
+    \itemL{30}{33}{d}{\Sxilinx}{Feedback for \ganttlf \xilinx RTL tools}{0:0:0.5}
         \xilinx will check that developped tutorial works well with \xilinx tools,
         and will propose corrections or enhancements if needed into a document.