- Timestamp:
- Feb 16, 2010, 10:02:02 PM (15 years ago)
- Location:
- anr
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
anr/section-4.4.tex
r195 r243 15 15 16 16 \begin{figure}\leavevmode\center 17 \hspace*{-. 6cm}\vspace{-1.5cm}17 \hspace*{-.4cm}%\vspace{-1.5cm} 18 18 \input{gantt1.tex} 19 \caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-4 )}19 \caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-4 and task-8)} 20 20 \end{figure} 21 21 22 22 \begin{figure}\leavevmode\center 23 \hspace*{-. 6cm}\vspace{-1.5cm}23 \hspace*{-.4cm}%\vspace{-1.5cm} 24 24 \input{gantt2.tex} 25 \caption{\label{gantt2}Gantt diagram of deliverables (task-5 to task-8)}25 \caption{\label{gantt2}Gantt diagram of deliverables (task-5, task-6 and task-7)} 26 26 \end{figure} 27 27 -
anr/task-1.tex
r237 r243 106 106 Final release of the former software (\specXcoachToVhdlI) and integration 107 107 of enhancements proposed in \novers{\specXilinxOptimization} deliverable. 108 \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optim .(1)}{0:3:0}108 \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimization (1)}{0:3:0} 109 109 \setMacroInAuxFile{specXilinxOptimization} 110 110 This deliverable consists in optimizing the VHDL generated from \xcoachplus format -
anr/task-2.tex
r237 r243 57 57 \setMacroInAuxFile{csgCoachArchTempl} 58 58 The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components. 59 \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optim .(2)}{0:2:0}59 \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimization (2)}{0:2:0} 60 60 This deliverable consists in optimizing the VHDL descriptions of the components of 61 61 the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the … … 71 71 The synthesizable VHDL description of the MWMR component corresponding to the 72 72 SystemC module of the former deliverable (\csgXilinxSystemC). 73 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optim .(3)}{0:0:1.5}73 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (3)}{0:0:1.5} 74 74 This deliverable consists in optimizing the MWMR VHDL description (deliverable 75 75 \novers{\csgXilinxSystemC}) of the \xilinx architectural template. … … 94 94 Final release of the tool that generates the VHDL description of the optimized 95 95 communication adapter and its corresponding SystemC module (\gautCOMMoptimization). 96 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optim .(4)}{0:0:1.5}96 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (4)}{0:0:1.5} 97 97 This deliverable consists in optimizing the communication adapter VHDL description (deliverable 98 98 \novers{\gautCOMMoptimization}). -
anr/task-4.tex
r223 r243 91 91 The frequency calibration software consists of a driver in the FPGA-SoC operating 92 92 system and of a control software. 93 \itemL{24}{27}{d}{\Sxilinx}{ Optimisation for \ganttlf \xilinx RTL tools(5)}{0:0:1.5}93 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (5)}{0:0:1.5} 94 94 This deliverable consists in optimizing the VHDL description provided in 95 95 \novers{\freqCalibrationVhdl}. -
anr/task-7.tex
r239 r243 59 59 \itemL{30}{36}{d}{\Supmc}{Tutorial}{2:1:1} 60 60 The final release of the tutorial. 61 \itemL{30}{33}{d}{\Sxilinx}{ Feedback for \ganttlf \xilinx RTL tools}{0:0:0.5}62 \xilinx will check that developped tutorial works well with \xilinx tools,61 \itemL{30}{33}{d}{\Sxilinx}{\xilinx feedback}{0:0:0.5} 62 \xilinx will check that the developped tutorial works well with \xilinx tools, 63 63 and will propose corrections or enhancements if needed into a document. 64 64 \end{livrable}
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