Changeset 244 for anr


Ignore:
Timestamp:
Feb 16, 2010, 10:08:08 PM (15 years ago)
Author:
coach
Message:

IA: typos

Location:
anr
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • anr/task-1.tex

    r243 r244  
    106106        Final release of the former software (\specXcoachToVhdlI) and integration
    107107        of enhancements proposed in \novers{\specXilinxOptimization} deliverable.
    108     \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimization (1)}{0:3:0}
     108    \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimisation (1)}{0:3:0}
    109109        \setMacroInAuxFile{specXilinxOptimization}
    110110        This deliverable consists in optimizing the VHDL generated from \xcoachplus format
  • anr/task-2.tex

    r243 r244  
    5757        \setMacroInAuxFile{csgCoachArchTempl}
    5858        The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
    59     \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimization (2)}{0:2:0}
     59    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
    6060       This deliverable consists in optimizing the VHDL descriptions of the components of
    6161       the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
     
    7171        The synthesizable VHDL description of the MWMR component corresponding to the
    7272        SystemC module of the former deliverable (\csgXilinxSystemC).
    73     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (3)}{0:0:1.5}
     73    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5}
    7474       This deliverable consists in optimizing the MWMR VHDL description (deliverable
    7575       \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
     
    9494       Final release of the tool that generates the VHDL description of the optimized
    9595       communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
    96     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (4)}{0:0:1.5}
     96    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5}
    9797       This deliverable consists in optimizing the communication adapter VHDL description (deliverable
    9898       \novers{\gautCOMMoptimization}).
  • anr/task-4.tex

    r243 r244  
    9191        The frequency calibration software consists of a driver in the FPGA-SoC operating
    9292        system and of a control software.
    93     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (5)}{0:0:1.5}
     93    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (5)}{0:0:1.5}
    9494       This deliverable consists in optimizing the VHDL description provided in
    9595       \novers{\freqCalibrationVhdl}.
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