- Timestamp:
- Feb 16, 2010, 10:08:08 PM (15 years ago)
- Location:
- anr
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
anr/task-1.tex
r243 r244 106 106 Final release of the former software (\specXcoachToVhdlI) and integration 107 107 of enhancements proposed in \novers{\specXilinxOptimization} deliverable. 108 \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimi zation (1)}{0:3:0}108 \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimisation (1)}{0:3:0} 109 109 \setMacroInAuxFile{specXilinxOptimization} 110 110 This deliverable consists in optimizing the VHDL generated from \xcoachplus format -
anr/task-2.tex
r243 r244 57 57 \setMacroInAuxFile{csgCoachArchTempl} 58 58 The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components. 59 \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimi zation (2)}{0:2:0}59 \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0} 60 60 This deliverable consists in optimizing the VHDL descriptions of the components of 61 61 the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the … … 71 71 The synthesizable VHDL description of the MWMR component corresponding to the 72 72 SystemC module of the former deliverable (\csgXilinxSystemC). 73 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimi zation (3)}{0:0:1.5}73 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5} 74 74 This deliverable consists in optimizing the MWMR VHDL description (deliverable 75 75 \novers{\csgXilinxSystemC}) of the \xilinx architectural template. … … 94 94 Final release of the tool that generates the VHDL description of the optimized 95 95 communication adapter and its corresponding SystemC module (\gautCOMMoptimization). 96 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimi zation (4)}{0:0:1.5}96 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5} 97 97 This deliverable consists in optimizing the communication adapter VHDL description (deliverable 98 98 \novers{\gautCOMMoptimization}). -
anr/task-4.tex
r243 r244 91 91 The frequency calibration software consists of a driver in the FPGA-SoC operating 92 92 system and of a control software. 93 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimi zation (5)}{0:0:1.5}93 \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (5)}{0:0:1.5} 94 94 This deliverable consists in optimizing the VHDL description provided in 95 95 \novers{\freqCalibrationVhdl}.
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